5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition - 2025-12-15

AN 847: Signal Tap Tutorial with Design Block Reuse for Arria 10 FPGA Development Board
Version
20.3
Product Type
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
Device Families > Arria Families > Arria 10
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software
Device Families > Arria Families
Resource Type
Documentation > Application Notes
ft:sourceName
DITA
Exporting the root partition in the Developer project does not include logic inside the reserved core or the SLD JTAG Bridge Host. The Consumer must add the SLD JTAG Bridge Host to the reserved core in the Consumer project.
  1. From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel® FPGA IP . Set the name as debug_host.
  2. Open the blinking_led_top.sv file, uncomment lines 26 to 31 and 48 to 55, and save the file.
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