Arria® 10 Hard Processor System Technical Reference Manual - Describes the features and functions of the Arria® 10 hard processor system. - 2026-01-16

Version: 25.3.1

1. Arria® 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
2.1. Features of the HPS
2.2. HPS Block Diagram and System Integration
2.2.1. HPS Block Diagram
2.2.2. Cortex-A9 MPCore
2.2.3. HPS Interfaces
2.2.3.1. HPS–FPGA Memory-Mapped Interfaces
2.2.3.2. Other HPS Interfaces
2.2.4. System Interconnect
2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect
2.2.4.1.1. SDRAM Adapter
2.2.4.1.2. SDRAM Scheduler
2.2.5. On-Chip Memory
2.2.5.1. On-Chip RAM
2.2.5.2. Boot ROM
2.2.6. Flash Memory Controllers
2.2.6.1. NAND Flash Controller
2.2.6.2. Quad SPI Flash Controller
2.2.6.3. SD/MMC Controller
2.2.7. Support Peripherals
2.2.7.1. Clock Manager
2.2.7.2. Reset Manager
2.2.7.3. Security Manager
2.2.7.4. System Manager
2.2.7.5. System Timers
2.2.7.6. System Watchdog Timers
2.2.7.7. DMA Controller
2.2.7.8. FPGA Manager
2.2.7.9. Error Checking and Correction Controller
2.2.8. Interface Peripherals
2.2.8.1. EMACs
2.2.8.2. USB Controllers
2.2.8.3. I2C Controllers
2.2.8.4. UARTs
2.2.8.5. SPI Master Controllers
2.2.8.6. SPI Slave Controllers
2.2.8.7. GPIO Interfaces
2.2.9. CoreSight Debug and Trace
2.2.10. Hard Processor System I/O Pin Multiplexing
2.3. Endian Support
2.4. Introduction to the Hard Processor System Address Map
2.4.1. HPS Address Spaces
2.4.1.1. SDRAM Address Space
2.4.1.2. MPU Address Space
2.4.1.3. FPGA Slaves Address Space
2.4.1.4. LWFPGA Slaves Address Space
2.4.1.5. L3 Address Space
2.4.2. HPS Peripheral Region Address Map
3. Clock Manager
3.1. Features of the Clock Manager
3.2. Clock Manager Block Diagram and System Integration
3.2.1. L4 Peripheral Clocks
3.2.2. Boot Clock
3.2.2.1. Updating PLL Settings without a System Reset
3.2.2.2. MPU Clock Scaling
3.3. Functional Description of the Clock Manager
3.3.1. Clock Manager Building Blocks
3.3.1.1. PLLs
3.3.1.2. FREF, FVCO, and FOUT Equations
3.3.1.3. Clock Gating
3.3.2. PLL Integration
3.3.3. Hardware-Managed and Software-Managed Clocks
3.3.4. Hardware Sequenced Clock Groups
3.3.5. Software Sequenced Clocks
3.3.6. Resets
3.3.7. Security
3.3.8. Interrupts
3.4. Clock Manager Address Map and Register Definitions
4. Reset Manager
4.1. Reset Manager Block Diagram and System Integration
4.1.1. Reset Controller
4.1.2. Security Reset Functions
4.1.3. Module Reset Signals
4.1.3.1. Modules Requiring Software Deassert
4.1.4. Slave Interface and Status Register
4.2. Functional Description of the Reset Manager
4.2.1. Reset Sequencing
4.2.1.1. Cold Reset Assertion Sequence
4.2.1.2. Warm Reset Assertion Sequence
4.2.1.3. Cold and Warm Reset Deassertion Sequence
4.2.2. Reset Pins
4.2.3. Reset Effects
4.2.4. Reset Handshaking
4.3. Reset Manager Address Map and Register Definitions
5. FPGA Manager
5.1. Features of the FPGA Manager
5.2. FPGA Manager Block Diagram and System Integration
5.3. Functional Description of the FPGA Manager
5.3.1. FPGA Configuration
5.3.2. FPGA Status
5.3.3. Error Message Extraction
5.3.4. Data AES Decryption
5.3.5. Boot Handshake
5.3.6. General Purpose I/O
5.3.7. Clock
5.3.8. Reset
5.4. FPGA Manager Address Map and Register Definitions
6. System Manager
6.1. Features of the System Manager
6.2. System Manager Block Diagram and System Integration
6.3. Functional Description of the System Manager
6.3.1. Boot Configuration and System Information
6.3.2. Additional Module Control
6.3.2.1. DMA Controller
6.3.2.2. NAND Flash Controller
6.3.2.3. EMAC
6.3.2.4. USB 2.0 OTG Controller
6.3.2.5. SD/MMC Controller
6.3.2.6. Watchdog Timer
6.3.3. Boot ROM Code
6.3.3.1. Controlling the Boot Memory Map Through the System Interconnect
6.3.4. FPGA Interface Enables
6.3.5. ECC and Parity Control
6.3.6. Preloader Handoff Information
6.3.7. Clocks
6.3.8. Resets
6.4. System Manager Address Map and Register Definitions
7. SoC Security
7.1. Security Manager
7.1.1. Security Manager Block Diagram
7.1.2. Functional Overview
7.1.3. Functional Description
7.1.3.1. Secure Initialization Overview
7.1.3.1.1. Secure Fuses
7.1.3.2. Security State
7.1.3.2.1. Security Check
7.1.3.2.2. Secure Serial Interface
7.1.3.3. Secure Debug
7.1.3.3.1. MPU
7.1.3.3.2. JTAG
7.1.3.4. Reset Manager
7.1.3.5. Clock Configuration
7.1.3.6. FPGA Security Features
7.1.3.7. Secure Boot
7.1.3.7.1. Boot Configuration
7.1.3.7.2. Secure Boot Process
7.1.3.7.3. Authentication and Decryption
7.1.3.8. Anti-Tamper
7.2. Security System Extensions
7.2.1. TrustZone®
7.2.1.1. Secure Partitioning
7.2.1.1.1. Secure Bus Accesses
7.2.1.1.2. Secure Cache Accesses
7.2.1.2. Virtual Processor Operation
7.2.2. Arria 10 HPS Secure Firewalls
7.2.2.1. Firewall Diagrams
7.2.2.2. Secure Transaction Protection
7.2.2.2.1. Peripheral and System Firewalls
7.2.2.2.1.1. Secure Transaction Example
7.2.2.2.1.2. Non-secure Transaction Configuration
7.2.2.2.2. HPS-to-FPGA Firewall
7.2.2.2.3. On-Chip RAM Firewall
7.2.2.2.3.1. On-Chip RAM Transaction Configuration
7.2.2.2.4. SDRAM Firewall
7.2.2.3. Privilege Filter
7.2.2.4. Master Security Policy
7.2.2.5. Secure Interconnect Reset
8. System Interconnect
8.1. About the System Interconnect
8.1.1. Features of the System Interconnect
8.1.2. System Interconnect Block Diagram and System Integration
8.1.2.1. System Interconnect Block Diagram
8.1.2.2. Connectivity
8.1.2.2.1. Arria 10 HPS Master-to-Slave Connectivity Matrix
8.1.2.2.2. On-Chip RAM
8.1.2.2.3. Peripherals Connections
8.1.2.2.4. System Connections
8.1.2.2.5. HPS-to-FPGA Bridge
8.1.2.2.6. SDRAM Connections
8.1.2.3. System Interconnect Architecture
8.1.2.3.1. SDRAM L3 Interconnect Architecture
7.2.2. Arria 10 HPS Secure Firewalls
8.1.4. About the Rate Adapters
8.1.5. About the SDRAM L3 Interconnect
8.1.5.1. Features of the SDRAM L3 Interconnect
8.1.5.2. SDRAM L3 Interconnect Block Diagram and System Integration
8.1.5.3. About the SDRAM Scheduler
8.1.6. About Arbitration and Quality of Service
8.1.7. About the Service Network
8.1.8. About the Observation Network
8.2. Functional Description of the System Interconnect
8.2.1. System Interconnect Address Spaces
8.2.1.1. Arria 10 HPS Available Address Maps
8.2.1.2. Arria 10 HPS L3 Address Space
8.2.1.3. MPU Address Space
8.2.1.4. SDRAM Address Space
8.2.1.5. Address Remapping
8.2.1.5.1. Memory Map Remap Bits
8.2.2. Secure Transaction Protection
8.2.3. System Interconnect Master Properties
8.2.3.1. Master Caching and Buffering Overrides
8.2.4. System Interconnect Slave Properties
8.2.5. System Interconnect Clocks
8.2.5.1. List of Main L3 Interconnect Clocks
8.2.5.2. List of SDRAM L3 Interconnect Clocks
8.2.6. System Interconnect Resets
8.2.7. Functional Description of the Rate Adapters
8.2.8. Functional Description of the Firewalls
8.2.8.1. Security
8.2.8.1.1. Slave Security
8.2.8.1.2. Master Security
8.2.9. Functional Description of the SDRAM L3 Interconnect
8.2.9.1. Functional Description of the SDRAM Scheduler
8.2.9.1.1. Monitors for Mutual Exclusion
8.2.9.1.1.1. Exclusive Access Support
8.2.9.1.2. Arbitration and Quality of Service in the SDRAM Scheduler
8.2.9.2. Functional Description of the SDRAM Adapter
8.2.9.2.1. ECC
8.2.9.2.1.1. ECC Write Behavior
8.2.9.2.1.2. ECC Read Behavior
8.2.9.2.2. SDRAM Adapter Interrupt Support
8.2.9.2.3. SDRAM Adapter Clocks
8.2.9.3. SDRAM L3 Firewalls
8.2.9.4. SDRAM L3 Interconnect Resets
8.2.10. Functional Description of the Arbitration Logic
8.2.11. Functional Description of the QoS Generators
8.2.11.1. QoS Generators in the Interconnect Architecture
8.2.11.2. QoS Mechanisms
8.2.11.2.1. Packet Urgency
8.2.11.2.2. Pressure Propagation
8.2.11.2.3. Hurry
8.2.11.3. QoS Generator Modes
8.2.11.3.1. Limiter Mode
8.2.11.3.2. Regulator Mode
8.2.11.3.3. Fixed Mode
8.2.12. Functional Description of the Observation Network
8.2.12.1. Probes
8.2.12.2. Packet Tracing, Profiling, and Statistics
8.2.12.2.1. Packet Filtering
8.2.12.2.2. Statistics Collection
8.2.12.2.3. Transaction Profiling
8.2.12.2.3.1. Profiling Transaction Latency
8.2.12.2.3.2. Profiling Pending Transactions
8.2.12.3. Packet Alarms
8.2.12.4. Error Logging
8.3. Configuring the System Interconnect
8.3.1. Configuring the Rate Adapters
8.3.2. Configuring the SDRAM Scheduler
8.3.2.1. FPGA Port Configuration
8.3.2.2. Memory Timing Configuration
8.3.2.3. Configuring SDRAM Burst Sizes
8.3.3. Configuring the Hard Memory Controller
8.3.3.1. SDRAM Adapter Memory Mapped Registers
8.3.3.2. Sharing I/Os between the EMIF and the FPGA
8.3.4. Configuring the Quality of Service Logic
8.3.4.1. Programming QoS Limiter Mode
8.3.4.2. Programming QoS Regulator Mode
8.3.4.3. Programming QoS Fixed Mode
8.3.4.4. Bandwidth and Saturation
8.3.4.5. QoS Generator Registers
8.3.4.6. QoS Programming Examples
8.3.4.6.1. Example: One Master Always Takes Precedence
8.3.4.6.2. Example: Tuning for Specific Throughput Requirements
8.4. System Interconnect Address Map and Register Definitions
9. HPS-FPGA Bridges
9.1. Features of the HPS-FPGA Bridges
9.2. Arria 10 HPS-FPGA Bridges Block Diagram and System Integration
9.3. Functional Description of the HPS-FPGA Bridges
9.3.1. Functional Description of the FPGA-to-HPS Bridge
9.3.1.1. FPGA-to-HPS Access to ACP
9.3.1.2. FPGA-to-HPS Bridge Slave Signals
9.3.2. Functional Description of the HPS-to-FPGA Bridge
9.3.2.1. HPS-to-FPGA Bridge Master Signals
9.3.3. Functional Description of the Lightweight HPS-to-FPGA Bridge
9.3.3.1. Lightweight HPS-to-FPGA Bridge Master Signals
9.3.4. Clocks and Resets
9.3.4.1. FPGA-to-HPS Bridge Clocks and Resets
9.3.4.2. HPS-to-FPGA Bridge Clocks and Resets
9.3.4.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets
9.3.4.4. Taking HPS-FPGA Bridges Out of Reset
9.3.5. Data Width Sizing
9.3.5.1. Ready Latency Support
9.4. HPS-FPGA Bridges Address Map and Register Definitions for Arria 10
10. Cortex®-A9 Microprocessor Unit Subsystem
10.1. Features of the Cortex-A9 MPU Subsystem
10.2. Cortex®-A9 MPU Subsystem Block Diagram and System Integration
10.2.1. Cortex®-A9 MPU Subsystem with System Interconnect
10.2.2. Cortex®-A9 MPU Subsystem Internals
10.3. Cortex®-A9 MPCore
10.3.1. Functional Description
10.3.2. Implementation Details
10.3.3. Cortex®-A9 Processor
10.3.3.1. Reset
10.3.4. Interactive Debugging Features
10.3.5. L1 Caches
10.3.5.1. Cache Latency
10.3.6. Preload Engine
10.3.7. Floating Point Unit
10.3.8. NEON™ Multimedia Processing Engine
10.3.8.1. Single Instruction, Multiple Data (SIMD) Processing
10.3.8.2. Features of the NEON™ MPE
10.3.9. Memory Management Unit
10.3.9.1. TLBs Supported By the MMU
10.3.9.2. TLB Features
10.3.9.3. The Boot Region
10.3.9.3.1. Boot ROM Mapping
10.3.9.4. The SDRAM Region
10.3.9.5. The FPGA Slaves Region
10.3.9.6. The HPS Peripherals Region
10.3.10. Performance Monitoring Unit
10.3.11. Arm® Cortex® -A9 MPCore Timers
10.3.11.1. Functional Description
10.3.11.2. Implementation Details
10.3.12. Generic Interrupt Controller
10.3.12.1. Functional Description
10.3.12.2. Implementation Details
10.3.12.2.1. GIC Interrupt Map for the Arria 10 SoC HPS
10.3.13. Global Timer
10.3.13.1. Functional Description
10.3.13.2. Implementation Details
10.3.14. Snoop Control Unit
10.3.14.1. Functional Description
10.3.14.1.1. Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
10.3.14.2. Implementation Details
10.3.15. Accelerator Coherency Port
10.3.15.1. AxUSER and AxCACHE Attributes
10.3.15.2. AxPROT Attributes
10.3.15.3. Cache Coherency for ACP Shared Requests
10.3.15.4. AXI Master Configuration for ACP Access
10.3.15.4.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses
10.3.15.4.2. Configuring AxUSER[4:0] Sideband Signals
10.3.15.4.3. Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses
10.3.15.5. Burst Sizes and Byte Strobes
10.3.15.5.1. Recommended Burst Types
10.3.15.6. Exclusive and Locked Accesses
10.3.15.7. Avoiding ACP Dependency Lockup
10.4. L2 Cache
10.4.1. Functional Description
10.4.1.1. Cache Controller Configuration
10.4.1.1.1. Implementation Details
10.4.1.1.1.1. L2 Cache Event Monitoring
10.4.1.2. Single Event Upset Protection
10.4.1.3. L2 Cache Parity
10.4.1.4. L2 Cache Lockdown Capabilities
10.4.1.5. L2 Cache Event Monitoring
10.4.1.6. L2 Cache Address Filtering
10.3.5.1. Cache Latency
10.5. CPU Prefetch
10.6. TrustZone®
7.2.1.1. Secure Partitioning
7.2.1.1.1. Secure Bus Accesses
7.2.1.1.2. Secure Cache Accesses
7.2.1.2. Virtual Processor Operation
10.6.3. Secure Debug
10.7. Debugging Modules
10.7.1. Program Trace
10.7.2. Event Trace
10.7.3. Cross-Triggering
10.8. Clocks
10.9. Cortex®-A9 MPU Subsystem Register Implementation
10.9.1. Cortex®-A9 MPU Subsystem Address Map for Arria 10
10.9.2. L2 Cache Controller Address Map for Arria 10
11. CoreSight™ Debug and Trace
11.1. Features of CoreSight™ Debug and Trace
11.2. Arm® CoreSight™ Documentation
11.3. CoreSight Debug and Trace Block Diagram and System Integration
11.4. Functional Description of CoreSight Debug and Trace
11.4.1. Debug Access Port
11.4.1.1. JTAG Connection
11.4.2. System Trace Macrocell
11.4.3. Trace Funnel
11.4.4. CoreSight Trace Memory Controller
11.4.4.1. Embedded Trace FIFO
11.4.4.2. Embedded Trace Router
11.4.5. AMBA® Trace Bus Replicator
11.4.6. Trace Port Interface Unit
11.4.7. Embedded Cross Trigger System
11.4.7.1. Cross Trigger Interface
11.4.7.2. Cross Trigger Matrix
11.4.8. Program Trace Macrocell
11.4.9. HPS Debug APB™ Interface
11.4.10. FPGA Interface
11.4.10.1. DAP
11.4.10.2. STM
11.4.10.3. FPGA-CTI
11.4.10.4. CTI-NoC
11.4.10.5. TPIU
11.4.11. Debug Clocks
11.4.12. Debug Resets
11.5. CoreSight™ Debug and Trace Programming Model
11.5.1. Coresight Component Address
11.5.2. STM Channels
11.5.3. CTI Trigger Connections to Outside the Debug System
11.5.3.1. CTI
11.5.3.2. FPGA-CTI
11.5.3.3. L3-CTI
11.5.4. Configuring Embedded Cross-Trigger Connections
11.5.4.1. Configuring Trigger Input 0
11.5.4.2. Triggering a Flush of Trace Data to the TPIU
11.5.4.3. Triggering an STM message
11.5.4.4. Triggering a Breakpoint on CPU 1
11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.6.1. stm Address Map
11.6.2. dap Address Map
12. Error Checking and Correction Controller
12.1. ECC Controller Features
12.2. ECC Supported Memories
12.3. ECC Controller Block Diagram and System Integration
12.4. ECC Controller Functional Description
12.4.1. Overview
12.4.2. ECC Structure
12.4.2.1. RAM and ECC Memory Organization Example
12.4.3. Memory Data Initialization
12.4.4. Indirect Memory Access
12.4.4.1. Watchdog Timer
12.4.4.2. Data Correction
12.4.4.3. Error Injection
12.4.4.4. Memory Testing
12.4.4.4.1. Peripheral Slave Interface Tests
12.4.4.4.2. Register Interface Tests
12.4.4.5. Error Checking and Correction Algorithm
12.4.5. Error Logging
12.4.5.1. Recent Error Address Registers
12.4.5.2. Single-Bit Error Occurrence
12.4.5.3. Single-Bit Error Look-Up Table
12.4.6. ECC Controller Interrupts
12.4.6.1. Single-Bit Error Interrupts
12.4.6.1.1. All Single-Bit Error Interrupt
12.4.6.1.2. LUT Overflow Interrupt
12.4.6.1.3. Counter Match Interrupt
12.4.6.2. Double-Bit Error Interrupt
12.4.6.3. Interrupt Testing
12.4.7. ECC Controller Initialization and Configuration
12.4.8. ECC Controller Clocks
12.4.9. ECC Controller Reset
12.5. ECC Controller Address Map and Register Descriptions
13. On-Chip Memory
13.1. On-Chip RAM
13.1.1. Features of the On-Chip RAM
13.1.2. On-Chip RAM Block Diagram and System Integration
13.1.3. Functional Description of the On-Chip RAM
13.1.3.1. On-Chip RAM Clocks
13.1.3.2. On-Chip RAM Resets
13.1.3.3. On-Chip RAM Initialization
13.1.3.4. On-Chip RAM Firewall
13.1.3.5. ECC Protection
13.2. Boot ROM
13.2.1. Features of the Boot ROM
13.2.2. Boot ROM Block Diagram and System Integration
13.2.3. Functional Description of the Boot ROM
13.2.3.1. Boot ROM Clocks
13.2.3.2. Boot ROM Resets
13.3. On-Chip Memory Address Map and Register Definitions
14. NAND Flash Controller
14.1. NAND Flash Controller Features
14.2. NAND Flash Controller Block Diagram and System Integration
14.3. NAND Flash Controller Signal Descriptions
14.4. Functional Description of the NAND Flash Controller
14.4.1. Discovery and Initialization
14.4.2. Bootstrap Interface
14.4.2.1. Bootstrap Setting Bits
14.4.3. Configuration by Host
14.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device
14.4.3.2. NAND Page Main and Spare Areas
14.4.4. Local Memory Buffer
14.4.5. Clocks
14.4.5.1. Clock Generation
14.4.5.2. Clock Enable
14.4.5.3. Clock Switching
14.4.6. Resets
14.4.6.1. Taking the NAND Flash Controller Out of Reset
14.4.7. Indexed Addressing
14.4.7.1. Register Map for Indexed Addressing
14.4.7.2. Indexed Addressing Host Usage
14.4.8. Command Mapping
14.4.8.1. MAP00 Commands
14.4.8.1.1. MAP00 Command Format
14.4.8.1.2. MAP00 Usage Limitations
14.4.8.2. MAP01 Commands
14.4.8.2.1. MAP01 Command Format
14.4.8.2.2. MAP01 Usage Limitations
14.4.8.3. MAP10 Commands
14.4.8.3.1. MAP10 Command Format
14.4.8.3.2. MAP10 Operations
14.4.8.3.3. MAP10 Usage Limitations
14.4.8.4. MAP11 Commands
14.4.8.4.1. MAP11 Control Format
14.4.8.4.2. MAP11 Usage Limitations
14.4.9. Data DMA
14.4.9.1. Multi-Transaction DMA Command
14.4.9.1.1. Command-Data Pair Formats
14.4.9.1.2. Using Multi-Transaction DMA Commands
14.4.9.2. Burst DMA Command
14.4.10. ECC
14.4.10.1. Correction Capability, Sector Size, and Check Bit Size
14.4.10.2. ECC Programming Modes
14.4.10.2.1. Main Area Transfer Mode
14.4.10.2.2. Spare Area Transfer Mode
14.4.10.2.3. Main+Spare Area Transfer Mode
14.4.10.3. Preserving Bad Block Markers
14.4.10.4. Error Correction Status
14.5. NAND Flash Controller Programming Model
14.5.1. Basic Flash Programming
14.5.1.1. NAND Flash Controller Optimization Sequence
14.5.1.2. Device Initialization Sequence
14.5.1.3. Device Operation Control
14.5.1.4. ECC Enabling
14.5.1.5. NAND Flash Controller Performance Registers
14.5.1.6. Interrupt and DMA Enabling
14.5.1.6.1. Order of Interrupt Status Bits Assertion
14.5.1.7. Timing Registers
14.5.1.8. Registers to Ignore
14.5.2. Flash-Related Special Function Operations
14.5.2.1. Erase Operations
14.5.2.1.1. Single Block Erase
14.5.2.1.2. Multi-Plane Erase
14.5.2.2. Lock Operations
14.5.2.2.1. Unlocking a Span of Memory Blocks
14.5.2.2.2. Locking All Memory Blocks
14.5.2.2.3. Setting Lock-Tight on All Memory Blocks
14.5.2.3. Transfer Mode Operations
14.5.2.3.1. transfer_spare_reg and MAP10 Transfer Mode Commands
14.5.2.3.2. Configure for Default Area Access
14.5.2.3.3. Configure for Spare Area Access
14.5.2.3.4. Configure for Main+Spare Area Access
14.5.2.4. Read-Modify-Write Operations
14.5.2.4.1. Read-Modify-Write Operation Flow
14.5.2.5. Copy-Back Operations
14.5.2.5.1. Copying a Memory Area (Single Plane)
14.5.2.5.2. Copying a Memory Area (Multi-Plane)
14.5.2.6. Pipeline Read-Ahead and Write-Ahead Operations
14.5.2.6.1. Pipeline Read-Ahead Function
14.5.2.6.1.1. Set Up a Single Area for Pipeline Read-Ahead
14.5.2.6.2. Pipeline Write-Ahead Function
14.5.2.6.2.1. Set Up a Single Area for Pipeline Write-Ahead
14.5.2.6.3. Other Supported Commands
14.6. NAND Flash Controller Address Map and Register Definitions
15. SD/MMC Controller
15.1. Features of the SD/MMC Controller
15.1.1. SD Card Support Matrix
15.1.2. MMC Support Matrix
15.2. SD/MMC Controller Block Diagram and System Integration
15.3. SD/MMC Controller Signal Description
15.4. Functional Description of the SD/MMC Controller
15.4.1. SD/MMC/CE-ATA Protocol
15.4.2. BIU
15.4.2.1. Slave Interface
15.4.2.2. Register Block
15.4.2.2.1. Registers Locked Out Pending Command Acceptance
15.4.2.3. Interrupt Controller Unit
15.4.2.3.1. Interrupt Setting and Clearing
15.4.2.4. FIFO Buffer
15.4.2.5. Internal DMA Controller
15.4.2.5.1. Internal DMA Controller Descriptors
15.4.2.5.2. Internal DMA Controller Descriptor Address
15.4.2.5.3. Internal DMA Controller Descriptor Fields
15.4.2.5.4. Host Bus Burst Access
15.4.2.5.5. Host Data Buffer Alignment
15.4.2.5.6. Buffer Size Calculations
15.4.2.5.7. Internal DMA Controller Interrupts
15.4.2.5.8. Internal DMA Controller Functional State Machine†
15.4.2.6. Abort During Internal DMA Transfer
15.4.2.7. Fatal Bus Error Scenarios
15.4.2.7.1. FIFO Buffer Overflow and Underflow
15.4.2.7.2. PBL and Watermark Levels
15.4.3. CIU
15.4.3.1. Command Path
15.4.3.1.1. Load Command Parameters
15.4.3.1.2. Send Command and Receive Response
15.4.3.1.3. Send Response to BIU
15.4.3.1.4. Driving P-bit to the CMD Pin
15.4.3.1.5. Polling the CCS
15.4.3.1.6. CCS Detection and Interrupt to Host Processor
15.4.3.1.7. CCS Timeout
15.4.3.1.8. Send CCSD Command
15.4.3.1.9. I/O transmission delay (NACIO Timeout)
15.4.3.2. Data Path
15.4.3.2.1. Data Transmit
15.4.3.2.1.1. Stream Data Transmit
15.4.3.2.1.2. Single Block Data
15.4.3.2.1.3. Multiple Block Data
15.4.3.2.2. Data Receive
15.4.3.2.2.1. Stream Data Read
15.4.3.2.2.2. Single-block Data Read
15.4.3.2.2.3. Multiple-block Data Read
15.4.3.2.3. Auto-Stop
15.4.3.2.3.1. Auto-Stop Generation for MMC Cards
15.4.3.2.3.2. Auto-Stop Generation for SD Cards
15.4.3.2.3.3. Auto-Stop Generation for SDIO Cards
15.4.3.2.4. Non-Data Transfer Commands that Use Data Path
15.4.3.3. Clock Control Block
15.4.3.4. Error Detection
15.4.3.4.1. Response†
15.4.3.4.2. Data Transmit†
15.4.3.4.3. Data Receive
15.4.4. Clocks
15.4.5. Resets
15.4.5.1. Taking the SD/MMC Controller Out of Reset
15.4.6. Voltage Switching
15.5. SD/MMC Controller Programming Model
15.6. SD/MMC Controller Address Map and Register Definitions
16. Quad SPI Flash Controller
16.1. Features of the Quad SPI Flash Controller
16.2. Quad SPI Flash Controller Block Diagram and System Integration
16.3. Quad SPI Flash Controller Signal Description
16.4. Functional Description of the Quad SPI Flash Controller
16.4.1. Overview
16.4.2. Data Slave Interface
16.4.2.1. Direct Access Mode
16.4.2.1.1. Data Slave Remapping Example
16.4.2.1.2. AHB®
16.4.2.2. Indirect Access Mode
16.4.2.2.1. Indirect Read Operation
16.4.2.2.2. Indirect Write Operation
16.4.2.2.3. Consecutive Reads and Writes
16.4.3. SPI Legacy Mode
16.4.4. Register Slave Interface
16.4.4.1. STIG Operation
16.4.5. Local Memory Buffer
16.4.6. DMA Peripheral Request Controller
16.4.7. Arbitration between Direct/Indirect Access Controller and STIG
16.4.8. Configuring the Flash Device
16.4.8.1. Write Request
16.4.9. XIP Mode
16.4.10. Write Protection
16.4.11. Data Slave Sequential Access Detection
16.4.12. Clocks
16.4.12.1. Clock Gating
16.4.13. Resets
16.4.13.1. Taking the Quad SPI Flash Controller Out of Reset
16.4.13.2. SRAM Initialization Procedure with ECC Enabled
16.4.14. Interrupts
16.5. Quad SPI Flash Controller Programming Model
16.5.1. Setting Up the Quad SPI Flash Controller
16.5.2. Indirect Read Operation with DMA Disabled
16.5.3. Indirect Read Operation with DMA Enabled
16.5.4. Indirect Write Operation with DMA Disabled
16.5.5. Indirect Write Operation with DMA Enabled
16.5.6. XIP Mode Operations
16.5.6.1. Entering XIP Mode
16.5.6.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP
16.5.6.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP
16.5.6.1.3. Winbond Quad SPI Flash Devices
16.5.6.1.4. Spansion Quad SPI Flash Devices
16.5.6.2. Exiting XIP Mode
16.5.6.3. XIP Mode at Power on Reset
16.6. Quad SPI Flash Controller Address Map and Register Definitions
17. DMA Controller
17.1. Features of the DMA Controller
17.2. DMA Controller Block Diagram and System Integration
17.3. Functional Description of the DMA Controller
17.3.1. Peripheral Request Interface
17.3.1.1. Peripheral Request Interface Mapping
17.4. DMA Controller Address Map and Register Definitions
17.4.1. DMA Controller Address Map and Register Definitions
18. Ethernet Media Access Controller
18.1. Features of the Ethernet MAC
18.1.1. MAC
18.1.2. DMA
18.1.3. Management Interface
18.1.4. Acceleration
18.1.5. PHY Interface
18.2. EMAC Block Diagram and System Integration
18.3. EMAC Signal Description
18.3.1. HPS EMAC I/O Signals
18.3.2. FPGA EMAC I/O Signals
18.3.3. PHY Management Interface
18.3.3.1. MDIO Interface
18.3.3.2. I2C External PHY Management Interface
18.4. EMAC Internal Interfaces
18.4.1. DMA Master Interface
18.4.2. Timestamp Interface
18.4.3. System Manager Configuration Interface
18.5. Functional Description of the EMAC
18.5.1. Transmit and Receive Data FIFO Buffers
18.5.2. DMA Controller
18.5.2.1. Descriptor Lists and Data Buffers†
18.5.2.2. Host Bus Burst Access
18.5.2.3. Host Data Buffer Alignment
18.5.2.3.1. Example: Buffer Read
18.5.2.3.2. Example: Buffer Write
18.5.2.4. Buffer Size Calculations
18.5.2.5. Transmission
18.5.2.5.1. TX DMA Operation: Default (Non-OSF) Mode
18.5.2.5.2. TX DMA Operation: OSF Mode
18.5.2.5.3. Transmit Frame Processing
18.5.2.5.4. Transmit Polling Suspended
18.5.2.6. Reception
18.5.2.6.1. Receive Descriptor Acquisition
18.5.2.6.2. Receive Frame Processing
18.5.2.6.3. Receive Process Suspended
18.5.2.7. Interrupts
18.5.2.8. Error Response to DMA
18.5.3. Descriptor Overview
18.5.3.1. Transmit Descriptor
18.5.3.2. Receive Descriptor
18.5.3.2.1. Receive Descriptor Field 0 (RDES0)
18.5.3.2.2. Receive Descriptor Field 1 (RDES1)
18.5.3.2.3. Receive Descriptor Fields (RDES2) and (RDES3)
18.5.3.2.3.1. Receive Descriptor Field 2 (RDES2)
18.5.3.2.3.2. Receive Descriptor Field 3 (RDES3)
18.5.3.2.4. Receive Descriptor Field 4 (RDES4)
18.5.3.2.5. Receive Descriptor Fields (RDES6) and (RDES7)
18.5.3.2.5.1. Receive Descriptor Field 6 (RDES6)
18.5.3.2.5.2. Receive Descriptor Field 7 (RDES7)
18.5.4. IEEE 1588-2002 Timestamps
18.5.4.1. Reference Timing Source
18.5.4.2. System Time Register Module
18.5.4.3. Transmit Path Functions
18.5.4.4. Receive Path Functions
18.5.4.5. Timestamp Error Margin
18.5.4.6. Frequency Range of Reference Timing Clock
18.5.5. IEEE 1588-2008 Advanced Timestamps
18.5.5.1. Peer-to-Peer PTP Transparent Clock (P2P TC) Message Support
18.5.5.2. Clock Types
18.5.5.2.1. Ordinary Clock
18.5.5.2.2. Boundary Clock
18.5.5.2.3. End-to-End Transparent Clock
18.5.5.2.4. Peer-to-Peer Transparent Clock
18.5.5.3. Reference Timing Source
18.5.5.4. Transmit Path Functions
18.5.5.5. Receive Path Functions
18.5.5.6. Auxiliary Snapshot
18.5.6. IEEE 802.3az Energy Efficient Ethernet
18.5.6.1. LPI Timers
18.5.7. Checksum Offload
18.5.8. Frame Filtering
18.5.8.1. Source Address or Destination Address Filtering
18.5.8.1.1. Unicast Destination Address Filter
18.5.8.1.2. Multicast Destination Address Filter
18.5.8.1.3. Hash or Perfect Address Filter
18.5.8.1.4. Broadcast Address Filter
18.5.8.1.5. Unicast Source Address Filter
18.5.8.1.6. Inverse Filtering Operation (Invert the Filter Match Result at Final Output)
18.5.8.1.7. Destination and Source Address Filtering Summary
18.5.8.2. VLAN Filtering
18.5.8.2.1. VLAN Tag-Based Filtering
18.5.8.2.2. VLAN Hash Filtering with a 16-Bit Hash Table
18.5.8.3. Layer 3 and Layer 4 Filters
18.5.8.3.1. Matched Frames
18.5.8.3.2. Unmatched Frames
18.5.8.3.3. NonTCP or UDP IP Frames
18.5.8.3.4. Layer 3 and Layer 4 Filters Register Set
18.5.8.3.5. Layer 3 Filtering
18.5.8.3.6. Layer 4 Filtering
18.5.9. Clocks and Resets
18.5.9.1. Clock Structure
18.5.9.2. Clock Gating for EEE
18.5.9.3. Reset
18.5.9.3.1. Taking the Ethernet MAC Out of Reset
18.5.10. Interrupts
18.6. Ethernet MAC Programming Model
18.6.1. System Level EMAC Configuration Registers
18.6.2. EMAC FPGA Interface Initialization
18.6.3. EMAC HPS Interface Initialization
18.6.4. DMA Initialization
18.6.5. EMAC Initialization and Configuration
18.6.6. Performing Normal Receive and Transmit Operation
18.6.7. Stopping and Starting Transmission
18.6.8. Programming Guidelines for Energy Efficient Ethernet
18.6.8.1. Entering and Exiting the TX LPI Mode
18.6.8.2. Gating Off the CSR Clock in the LPI Mode
18.6.8.2.1. Gating Off the CSR Clock in the RX LPI Mode
18.6.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.6.9.1. Generating a Single Pulse on PPS
18.6.9.2. Generating a Pulse Train on PPS
18.6.9.3. Generating an Interrupt without Affecting the PPS
18.7. Ethernet MAC Address Map and Register Definitions
19. USB 2.0 OTG Controller
19.1. Features of the USB OTG Controller
19.1.1. Supported PHYS
19.2. USB OTG Controller Block Diagram and System Integration
19.3. USB 2.0 ULPI PHY Signal Description
19.4. Functional Description of the USB OTG Controller
19.4.1. USB OTG Controller Block Description
19.4.1.1. Master Interface
19.4.1.2. Slave Interface
19.4.1.2.1. Slave Interface CSR Unit
19.4.1.3. Application Interface Unit
19.4.1.4. Packet FIFO Controller
19.4.1.5. SPRAM
19.4.1.6. MAC
19.4.1.6.1. USB Transactions
19.4.1.6.2. Host Protocol
19.4.1.6.3. Device Protocol
19.4.1.6.4. OTG Protocol
19.4.1.7. Wakeup and Power Control
19.4.1.8. PHY Interface Unit
19.4.1.9. DMA
19.4.2. Local Memory Buffer
19.4.3. Clocks
19.4.3.1. Clock Gating
19.4.4. Resets
19.4.4.1. Reset Requirements
19.4.4.2. Hardware Reset
19.4.4.3. Software Reset
19.4.4.4. Taking the USB 2.0 OTG Controller Out of Reset
19.4.5. Interrupts
19.5. USB OTG Controller Programming Model
19.5.1. Enabling ECC
19.5.2. Enabling SPRAM ECCs
19.5.3. Host Operation
19.5.3.1. Host Initialization
19.5.3.2. Host Transaction
19.5.4. Device Operation
19.5.4.1. Device Initialization
19.5.4.2. Device Transaction
19.5.4.2.1. IN Transactions
19.5.4.2.2. OUT Transactions
19.5.4.2.3. Control Transfers
19.6. USB 2.0 OTG Controller Address Map and Register Definitions
20. SPI Controller
20.1. Features of the SPI Controller
20.2. SPI Block Diagram and System Integration
20.2.1. SPI Block Diagram
20.3. SPI Controller Signal Description
20.3.1. Interface to HPS I/O
20.3.2. FPGA Routing
20.4. Functional Description of the SPI Controller
20.4.1. Protocol Details and Standards Compliance
20.4.2. SPI Controller Overview
20.4.2.1. Serial Bit-Rate Clocks
20.4.2.1.1. SPI Master Bit-Rate Clock
20.4.2.1.2. SPI Slave Bit-Rate Clock
20.4.2.2. Transmit and Receive FIFO Buffers
20.4.2.3. SPI Interrupts
20.4.3. Transfer Modes
20.4.3.1. Transmit and Receive
20.4.3.2. Transmit Only
20.4.3.3. Receive Only
20.4.3.4. EEPROM Read
20.4.4. SPI Master
20.4.4.1. RXD Sample Delay
20.4.4.2. Data Transfers
20.4.4.3. Master SPI and SSP Serial Transfers
20.4.4.4. Master Microwire Serial Transfers
20.4.5. SPI Slave
20.4.5.1. Slave SPI and SSP Serial Transfers
20.4.5.2. Serial Transfers
20.4.5.3. Glue Logic for Master Port ss_in_n
20.4.6. Partner Connection Interfaces
20.4.6.1. Motorola SPI Protocol
20.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP)
20.4.6.3. National Semiconductor Microwire Protocol
20.4.7. DMA Controller Interface
20.4.8. Slave Interface
20.4.8.1. Control and Status Register Access
20.4.8.2. Data Register Access
20.4.9. Clocks and Resets
20.4.9.1. Clock Gating
20.4.9.2. Taking the SPI Controller Out of Reset
20.5. SPI Programming Model
20.5.1. Master SPI and SSP Serial Transfers
20.5.2. Master Microwire Serial Transfers
20.5.3. Slave SPI and SSP Serial Transfers
20.5.4. Slave Microwire Serial Transfers
20.5.5. Software Control for Slave Selection
20.5.5.1. Example: Slave Selection Software Flow for SPI Master
20.5.5.2. Example: Slave Selection Software Flow for SPI Slave
20.5.6. DMA Controller Operation
20.5.6.1. Transmit FIFO Buffer Underflow
20.5.6.2. Transmit FIFO Watermark
20.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64
20.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
20.5.6.3. Transmit FIFO Buffer Overflow
20.5.6.4. Receive FIFO Buffer Overflow
20.5.6.5. Choosing Receive Watermark Level
20.5.6.6. Receive FIFO Buffer Underflow
20.6. SPI Controller Address Map and Register Definitions
21. I2C Controller
21.1. Features of the I2C Controller
21.2. I2C Controller Block Diagram and System Integration
21.3. I2C Controller Signal Description
21.4. Functional Description of the I2C Controller
21.4.1. Feature Usage
21.4.2. Behavior
21.4.2.1. START and STOP Generation
21.4.2.2. Combined Formats
21.4.3. Protocol Details
21.4.3.1. START and STOP Conditions
21.4.3.2. Addressing Slave Protocol
21.4.3.2.1. 7-Bit Address Format
21.4.3.2.2. 10-Bit Address Format
21.4.3.3. Transmitting and Receiving Protocol
21.4.3.3.1. Master-Transmitter and Slave-Receiver
21.4.3.3.2. Master-Receiver and Slave-Transmitter
21.4.3.4. START BYTE Transfer Protocol
21.4.4. Multiple Master Arbitration
21.4.4.1. Clock Synchronization
21.4.5. Clock Frequency Configuration
21.4.5.1. Minimum High and Low Counts
21.4.5.1.1. Calculating High and Low Counts
21.4.6. SDA Hold Time
21.4.7. DMA Controller Interface
21.4.8. Clocks
21.4.9. Resets
21.4.9.1. Taking the I2C Controller Out of Reset
21.5. I2C Controller Programming Model
21.5.1. Slave Mode Operation
21.5.1.1. Initial Configuration
21.5.1.2. Slave-Transmitter Operation for a Single Byte
21.5.1.3. Slave-Receiver Operation for a Single Byte
21.5.1.4. Slave-Transfer Operation for Bulk Transfers
21.5.1.5. Slave Programming Model
21.5.2. Master Mode Operation
21.5.2.1. Initial Configuration
21.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update
21.5.2.3. Master Transmit and Master Receive
21.5.2.4. Master Programming Model
21.5.3. Disabling the I2C Controller
21.5.4. Abort Transfer
21.5.5. DMA Controller Operation
21.5.5.1. Transmit FIFO Underflow
21.5.5.2. Transmit Watermark Level
21.5.5.3. Transmit FIFO Overflow
21.5.5.4. Receive FIFO Overflow
21.5.5.5. Receive Watermark Level
21.5.5.6. Receive FIFO Underflow
21.6. I 2 C Controller Address Map and Register Definitions
22. UART Controller
22.1. UART Controller Features
22.2. UART Controller Block Diagram and System Integration
22.3. UART Controller Signal Description
22.3.1. HPS I/O Pins
22.3.2. FPGA Routing
22.4. Functional Description of the UART Controller
22.4.1. FIFO Buffer Support
22.4.2. UART(RS232) Serial Protocol
22.4.3. Automatic Flow Control
22.4.3.1. RTC Flow Control Trigger
22.4.3.2. Automatic RTS mode
22.4.3.3. Automatic CTS mode
22.4.4. Clocks
22.4.5. Resets
22.4.5.1. Taking the UART Controller Out of Reset
22.4.6. Interrupts
22.4.6.1. Programmable THRE Interrupt
22.5. DMA Controller Operation
22.5.1. Transmit FIFO Underflow
22.5.2. Transmit Watermark Level
22.5.2.1. IIR_FCR.TET = 1
22.5.2.2. IIR_FCR.TET = 3
22.5.3. Transmit FIFO Overflow
22.5.4. Receive FIFO Overflow
22.5.5. Receive Watermark Level
22.5.6. Receive FIFO Underflow
22.6. UART Controller Address Map and Register Definitions
23. General-Purpose I/O Interface
23.1. Features of the GPIO Interface
23.2. GPIO Interface Block Diagram and System Integration
23.3. Functional Description of the GPIO Interface
23.3.1. Debounce Operation
23.3.2. Pin Directions
23.3.3. Taking the GPIO Interface Out of Reset
23.4. GPIO Interface Programming Model
23.5. General-Purpose I/O Interface Address Map and Register Definitions
24. Timer
24.1. Features of the Timer
24.2. Timer Block Diagram and System Integration
24.3. Functional Description of the Timer
24.3.1. Clocks
24.3.2. Resets
24.3.3. Interrupts
24.4. Timer Programming Model
24.4.1. Initialization
24.4.2. Enabling the Timer
24.4.3. Disabling the Timer
24.4.4. Loading the Timer Countdown Value
24.4.5. Servicing Interrupts
24.4.5.1. Clearing the Interrupt
24.4.5.2. Checking the Interrupt Status
24.4.5.3. Masking the Interrupt
24.5. Timer Address Map and Register Definitions
25. Watchdog Timer
25.1. Features of the Watchdog Timer
25.2. Watchdog Timer Block Diagram and System Integration
25.3. Functional Description of the Watchdog Timer
25.3.1. Watchdog Timer Counter
25.3.2. Watchdog Timer Pause Mode
25.3.3. Watchdog Timer Clocks
25.3.4. Watchdog Timer Resets
25.3.4.1. Taking the Watchdog Timer Out of Reset
25.4. Watchdog Timer Programming Model
25.4.1. Setting the Timeout Period Values
25.4.2. Selecting the Output Response Mode
25.4.3. Enabling and Initially Starting a Watchdog Timer
25.4.4. Reloading a Watchdog Counter
25.4.5. Pausing a Watchdog Timer
25.4.6. Disabling and Stopping a Watchdog Timer
25.4.7. Watchdog Timer State Machine
25.5. Watchdog Timer Address Map and Register Definitions
26. Hard Processor System I/O Pin Multiplexing
26.1. Features of the HPS I/O Block
26.2. HPS I/O Block Diagram and System Integration
26.3. Functional Description of the HPS I/O
26.3.1. Dedicated I/O Pins
26.3.1.1. Warm Reset Pin
26.3.1.2. Boot Pins
26.3.2. Shared I/O Pins
26.3.3. FPGA Access
26.3.4. Control Registers
26.3.4.1. Dedicated Pin MUX Registers
26.3.4.2. Dedicated Configuration Registers
26.3.4.3. Shared Pin MUX Registers
26.3.4.4. FPGA Access MUX Registers
26.3.5. Configuring HPS I/O Multiplexing
26.3.5.1. Configuring Multiplexing at System Generation
26.3.5.2. Configuring Multiplexing at Boot Time
26.4. Test Considerations
26.5. I/O Pin MUX Address Map and Register Definitions
27. Introduction to the HPS Component
27.1. MPU Subsystem
27.2. Arm® CoreSight™ Debug Components
27.3. Interconnect
27.4. HPS-to-FPGA Interfaces
27.5. Memory Controllers
27.5.1. HPS SDRAM Controller
27.5.1.1. HMC and HPS Connectivity
27.5.1.2. Clocks
27.5.1.3. Resets
27.6. Support Peripherals
27.7. Interface Peripherals
27.8. On-Chip Memories
28. Instantiating the HPS Component
28.1. Using the HPS Parameter Editor
28.2. FPGA Interfaces
28.2.1. General Interfaces
28.2.2. FPGA-to-HPS SDRAM Interface
28.2.3. DMA Peripheral Request
28.2.4. Security Manager
28.2.5. Interrupts
28.2.6. AXI Bridges
28.3. Configuring HPS Clocks and Resets
28.3.1. Alternate Clock Source from FPGA
28.3.2. User Clocks
28.3.2.1. User Clock Parameters
28.3.2.2. Clock Frequency Usage
28.3.3. Reset Interfaces
28.3.4. Peripheral FPGA Clocks
28.4. Configuring Peripheral Pin Multiplexing
28.4.1. Configuring Peripherals
28.4.1.1. Boot Source
28.4.2. Connecting Unassigned Pins to GPIO
28.4.3. Peripheral Signals Routed to FPGA
28.5. Configuring the External Memory Interface
28.6. Using the Address Span Extender Component
28.7. Generating and Compiling the HPS Component
29. HPS Component Interfaces
29.1. Memory-Mapped Interfaces
29.1.1. FPGA-to-HPS Bridge
29.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges
29.1.3. FPGA-to-HPS SDRAM Interface
29.1.4. EMIF Conduit
29.2. Clocks
29.2.1. Alternative Clock Inputs to HPS PLLs
29.2.2. User Clocks
29.2.3. AXI Bridge FPGA Interface Clocks
29.2.4. SDRAM Clocks
29.2.5. Peripheral FPGA Clocks
29.3. Resets
29.3.1. HPS-to-FPGA Reset Interfaces
29.3.2. HPS External Reset Request
29.3.3. Peripheral Reset Interfaces
29.4. Debug and Trace Interfaces
29.4.1. FPGA System Trace Macrocell Events Interface
29.4.2. FPGA Cross Trigger Interface
29.4.3. Debug APB™ Interface
29.5. Peripheral Signal Interfaces
29.5.1. Platform Designer (Standard) Peripheral Port Interface Mapping
29.5.1.1. NAND Flash Controller Interface
29.5.1.2. SD/MMC Controller Interface
29.5.1.3. Quad SPI Flash Controller Interface
29.5.1.4. Ethernet Media Access Controller Interface
29.5.1.5. USB 2.0 OTG Controller Interface
29.5.1.6. SPI Controller Interface
29.5.1.7. I2C Controller Interface
29.5.1.8. UART Interface
29.5.2. DMA Controller Interface
29.6. Other Interfaces
29.6.1. MPU Standby and Event Interfaces
29.6.2. General Purpose Signals
29.6.3. FPGA-to-HPS Interrupts
29.6.4. Boot from FPGA Interface
29.6.5. Security Manager
30. Simulating the HPS Component
30.1. Simulation Flows
30.1.1. Setting Up the HPS Component for Simulation
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
30.1.1. Setting Up the HPS Component for Simulation
30.1.2. Generating the HPS Simulation Model in Platform Designer (Standard)
30.1.3. Running the Simulations
30.1.3.1. Running HPS RTL Simulation
30.1.3.2. Running HPS Post-Fit Simulation
30.1.3.2.1. Post-Fit Simulation Files
30.1.3.2.2. BFM API Hierarchy Format
30.2. Clock and Reset Interfaces
30.2.1. Clock Interface
30.2.2. Reset Interface
30.3. FPGA-to-HPS AXI Slave Interface
30.4. HPS-to-FPGA AXI Master Interface
30.5. Lightweight HPS-to-FPGA AXI Master Interface
30.6. HPS-to-FPGA MPU Event Interface
30.7. Interrupts Interface
30.8. HPS-to-FPGA Debug APB™ Interface
30.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
30.10. HPS-to-FPGA Cross-Trigger Interface
30.11. FPGA-to-HPS DMA Handshake Interface
30.12. Boot from FPGA Interface
30.13. Security Manager Anti-Tamper Signals Interface
30.14. EMIF Conduit
30.15. Pin MUX and Peripherals
30.15.1. HPS Conduit Interfaces Connecting to the HPS I/O
30.15.2. HPS Conduit Interfaces Connecting to the FPGA
A. Booting and Configuration
A.1. Boot Overview
A.2. FPGA Configuration Overview
A.3. Booting and Configuration Options
A.4. Boot Definitions
A.4.1. Reset
A.4.2. Boot ROM
A.4.3. Boot Select
A.4.3.1. Boot Source I/O Pins
A.4.3.2. Boot Fuses
A.4.4. Flash Memory Devices for Booting
A.4.4.1. SD/MMC Flash Devices
A.4.4.1.1. Default Settings of the SD/MMC Controller
A.4.4.1.2. CSEL Settings for the SD/MMC Controller
A.4.4.2. NAND Flash Devices
A.4.4.2.1. NAND Flash Driver Features Supported in the Boot ROM Code
A.4.4.2.2. CSEL Settings for the NAND Controller
A.4.4.3. Quad SPI Flash Devices
A.4.4.3.1. Quad SPI Controller Default Settings
A.4.4.3.2. Quad SPI Flash Delay Configuration
A.4.4.3.3. Quad SPI Controller CSEL Settings
A.4.5. Clock Select
A.4.6. I/O Configuration
A.4.6.1. I/O State
A.4.7. L4 Watchdog 0 Timer
A.4.8. Second-Stage Boot Loader
A.4.9. Secure Boot
A.5. Boot ROM Flow
A.6. Second-Stage Boot Flow
A.6.1. Typical Boot Flow (Non-Secure)
A.6.2. Secure Boot Flow
A.6.3. HPS State on Entry to the Second-Stage Boot Loader
A.6.4. Loading the Second-Stage Boot Loader Image
A.7. FPGA Configuration
A.7.1. Full FPGA Configuration Flow Through HPS
A.7.2. Early I/O Release FPGA Configuration Flow Through HPS
A.7.2.1. Handling an FPGA Configuration Failure after Early I/O Release
A.7.3. Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager
A.8. FPGA Reconfiguration
A.8.1. Full FPGA Reconfiguration
A.8.2. Arria 10 SoC FPGA Partial Reconfiguration Sequence Through FPGA Manager
nocp-doc-link/683364.html
https:/www.intel.com/content/www/us/en/programmable/hps/arria-v/hps.html
http:/www.altera.com/literature/manual/mnl_avalon_spec.html
http:/www.bosch-semiconductors.de/en/ubk_semiconductors/homepage/homepage_1.html
http:/www.altera.com/literature/hb/external-memory/emi_fd_hard_memory.html
http:/www.altera.com/literature/hb/external-memory/emi_parameters.html
http:/www.altera.com/support/kdb/solutions/fb100506.html
http:/www.altera.com/literature/hb/qts/qsys_interconnect.html
http:/www.altera.com/literature/hb/arria-v/av_52007.html
http:/www.altera.com/literature/ug/ug_altiobuf.html
http:/www.usb.org/home.html

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