EPCQ-L Serial Configuration Devices Datasheet - 2018-05-18

EPCQ-L Serial Configuration Devices Datasheet
Supported Devices
Features
Operating Conditions
Absolute Maximum Ratings
Recommended Operating Conditions
DC Operating Conditions
ICC Supply Current
Capacitance
Pin Information
EPCQ-L Device Pin Description
Device Package and Ordering Code
Package
Ordering Code
Memory Array Organization
Address Range for EPCQ-L256
Address Range for EPCQ-L512
Address Range for EPCQ-L1024
Memory Operations
Timing Requirements
Addressing Mode
Registers
Status Register
Read Status Register Operation (05h)
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Write Status Register Operation (01h)
Flag Status Register
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register
Read Non-Volatile Configuration Register Operation (B5h)
Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)
Write Enable Operation (06h)
Write Disable Operation (04h)
Read Bytes Operation (03h)
Fast Read Operation (Bh)
Extended Quad Input Fast Read Operation (EBh)
Read Device Identification Operation (9Eh or 9Fh)
Write Bytes Operation (02h)
Extended Quad Input Fast Write Bytes Operation (12h)
Erase Bulk Operation (C7h)
Erase Die Operation (C4h)
Erase Sector Operation (D8h)
Power Mode
Timing Information
Write Operation Timing
Read Operation Timing
Programming and Configuration File Support
Document Revision History for EPCQ-L Serial Configuration Devices Datasheet

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