1.2. DSP Design Flow in FPGAs - DSP Builder for Altera FPGAs simplifies hardware implementation of DSP functions, provides a system-level verification tool to the system engineer who is not necessarily familiar with HDL design flow, and allows the system engineer to implement DSP functions in FPGAs without learning HDL. - 2025-12-15

Introduction to DSP Builder for Altera FPGAs

Version
19.3
Traditionally, system engineers use a hardware flow based on an HDL, such as Verilog HDL or VHDL, to implement DSP systems in FPGAs. Altera tools such as DSP Builder, enable you to follow a software-based design flow while targeting FPGAs. DSP Builder for Altera® FPGAs simplifies hardware implementation of DSP functions, provides a system-level verification tool to the system engineer who is not necessarily familiar with HDL design flow, and allows the system engineer to implement DSP functions in FPGAs without learning HDL. DSP Builder for Altera® FPGAs provides an interface from Simulink directly to the FPGA hardware. Additionally, you can incorporate the designs created by DSP Builder for Altera® FPGAs into a Platform Designer system for a complete DSP system implementation.