Embedded Design Handbook - This document describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools, and recommends design styles and practices for developing, debugging, and optimizing Nios II processor-based embedded systems using Intel provided tools. - 2023-08-28
Product Type
Device Families > Agilex Families
Device Families > Cyclone Families > Cyclone IV
Device Families > Agilex Families > Agilex 7
Device Families > Stratix Families > Stratix IV
Device Families > Stratix Families
Device Families > Cyclone Families > Cyclone V
Device Families > Stratix Families > Stratix V
Device Families > Agilex Families > Agilex 7 > I-Series
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX
Device Families > Cyclone Families > Cyclone II
Device Families > Arria Families > Arria V
Device Families > Cyclone Families > Cyclone 10
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Arria Families > Arria II
Device Families > Arria Families > Arria 10
Device Families > MAX Families > MAX 10
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Cyclone Families > Cyclone III
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 LP
Device Families > Stratix Families > Stratix 10
Device Families > Cyclone Families
Device Families > Stratix Families > Stratix III
Device Families > Arria Families
Device Families > MAX Families
Resource Type
Documentation > User Guides
Source Name
DITA
Product Discontinuance Notification
1. Introduction
1.1. Document Revision History for Embedded Design Handbook
2. First Time Designer's Guide
2.1. FPGAs and Soft-Core Processors
2.2. Embedded System Design
2.3. Embedded Design Resources
2.3.1. Intel Embedded Support
2.3.2. Intel Embedded Training
2.3.3. Intel Embedded Documentation
2.3.4. Third Party Intellectual Property
2.4. Intel Embedded Glossary
2.5. First Time Designer's Guide Revision History
3. Hardware System Design with Intel Quartus Prime and Platform Designer
3.1. FPGA Hardware Design
3.1.1. Connecting Your FPGA Design to Your Hardware
3.1.2. Connecting Signals to your Platform Designer System
3.1.3. Constraining Your FPGA-Based Design
3.2. System Design with Platform Designer
3.2.1. Intel System on a Programmable Chip (Platform Designer) Solutions
3.2.2. Platform Designer Design
3.3. Interfacing an External Processor to an Intel FPGA
3.3.1. Configuration Options
3.3.2. RapidIO Interface
3.3.3. PCI Express Interface
3.3.4. PCI Interface
3.3.5. Serial Protocol Interface (SPI)
3.3.6. Custom Bridge Interfaces
3.4. Avalon-MM Byte Ordering
3.4.1. Endianness
3.4.1.1. Hardware Endianness
3.4.1.2. Software Endianness
3.4.2. Avalon -MM Interface Ordering
3.4.2.1. Dynamic Bus Sizing DMA Examples
3.4.3. Nios II Processor Data Accesses
3.4.4. Adapting Processor Masters to be Avalon-MM Compliant
3.4.4.1. PowerPC Bus Byte Ordering
3.4.4.2. ARM BE-32 Bus Byte Ordering
3.4.4.3. ARM BE-8 Bus Byte Ordering
3.4.4.4. Other Processor Bit and Byte Orders
3.4.4.5. Arithmetic Byte Reordering
3.4.5. System-Wide Design Recommendations
3.4.5.1. System-Wide Arithmetic Byte Ordering
3.4.5.2. System-Wide Arithmetic Byte Reordering in Software
3.5. Memory System Design
3.5.1. Memory Types
3.5.1.1. Volatile Memory
3.5.1.2. Non-Volatile Memory
3.5.2. On-Chip Memory
3.5.2.1. Advantages
3.5.2.2. Disadvantages
3.5.2.3. Best Applications
3.5.2.3.1. Cache
3.5.2.3.2. Tightly Coupled Memory
3.5.2.3.3. Look Up Tables
3.5.2.3.4. FIFO
3.5.2.4. Poor Applications
3.5.2.5. On-Chip Memory Types
3.5.2.6. Best Practices
3.5.3. External SRAM
3.5.3.1. Advantages
3.5.3.2. Disadvantages
3.5.3.3. Best Applications
3.5.3.4. Poor Applications
3.5.3.5. External SRAM Types
3.5.3.6. Best Practices
3.5.4. Flash Memory
3.5.4.1. Advantages
3.5.4.2. Disadvantages
3.5.4.3. Typical Applications
3.5.4.4. Poor Applications
3.5.4.5. Flash Types
3.5.5. SDRAM
3.5.5.1. Advantages
3.5.5.2. Disadvantages
3.5.5.3. Best Applications
3.5.5.4. Poor Applications
3.5.5.5. SDRAM Types
3.5.5.6. SDRAM Controller Types Available From Intel
3.5.5.7. Best Practices
3.5.5.7.1. Half-Rate Mode
3.5.5.7.2. Full-Rate Mode
3.5.5.7.3. Sequential Access
3.5.5.7.4. Bursting
3.5.5.7.5. SDRAM Minimum Frequency
3.5.5.7.6. SDRAM Device Speed
3.5.6. Case Study
3.5.6.1. Application Description
3.5.6.2. Initial Memory Partitioning
3.5.6.3. Optimized Memory Partitioning
3.5.6.3.1. Add an External SRAM for Input Buffers
3.5.6.3.2. Add On-Chip Memory for Video Line Buffers
3.6. Nios II Hardware Development Tutorial
3.6.1. Software and Hardware Requirements
3.6.2. Intel FPGA IP Evaluation Mode
3.6.3. Nios II Design Example
3.6.4. Nios II System Development Flow
3.6.4.1. Analyzing System Requirements
3.6.4.2. Defining and Generating the System in Platform Designer
3.6.4.3. Integrating the Platform Designer System into the Intel Quartus Prime Project
3.6.4.4. Developing Software with the Nios II Software Build Tools for Eclipse
3.6.4.5. Running and Debugging Software on the Target Board
3.6.4.6. Varying the Development Flow
3.6.5. Creating the Design Example
3.6.5.1. Install the Design Files
3.6.5.2. Analyze System Requirements
3.6.5.3. Start the Intel Quartus Prime Software and Open the Example Project
3.6.5.4. Create a New Platform Designer System
3.6.5.5. Define the System in Platform Designer
3.6.5.5.1. Specify Target FPGA and Clock Settings
3.6.5.5.2. Add the On-Chip Memory
3.6.5.5.3. Add the Nios II Processor Core
3.6.5.5.4. Add the JTAG UART
3.6.5.5.5. Add the Interval Timer
3.6.5.5.6. Add the System ID Peripheral
3.6.5.5.7. Add the PIO
3.6.5.5.8. Specify Base Addresses and Interrupt Request Priorities
3.6.5.5.9. Generate the Platform Designer System
3.6.5.6. Integrate the Platform Designer System into the Intel Quartus Prime Project
3.6.5.6.1. Instantiate the Platform Designer System Module in the Intel Quartus Prime Project
3.6.5.6.2. Add IP Variation File
3.6.5.6.3. Assign FPGA Device
3.6.5.6.4. Assign FPGA Pin Locations
3.6.5.6.5. Set Timing
3.6.5.6.6. Compile the Intel Quartus Prime Project and Verify Timing
3.6.5.7. Download the Hardware Design to the Target FPGA
3.6.5.8. Develop Software Using the Nios II SBT for Eclipse
3.6.5.8.1. Create a New Nios II Application and BSP from Template
3.6.5.8.2. Compile the Project
3.6.5.9. Run the Program on Target Hardware
3.7. Platform Designer System Design Tutorial
3.7.1. Software and Hardware Requirements
3.7.2. Download and Install the Tutorial Design Files
3.7.3. Open the Tutorial Project
3.7.4. Creating Platform Designer Systems
3.7.4.1. Create a Data Pattern Generator Platform Designer System
3.7.4.1.1. Create a New Platform Designer System and Set up the Clock Source
3.7.4.1.2. Add a Pipeline Bridge
3.7.4.1.3. Add a Custom Pattern Generator
3.7.4.1.4. Add a PRBS Pattern Generator
3.7.4.1.5. Add a Two-to-One Streaming Multiplexer
3.7.4.1.6. Verify the Memory Address Map
3.7.4.1.7. Connect the Reset Signals
3.7.4.1.8. Save the System
3.7.4.2. Create a Data Pattern Checker Platform Designer System
3.7.4.2.1. Create a New Platform Designer System and Set Up the Clock Source
3.7.4.2.2. Add a Pipeline Bridge
3.7.4.2.3. Add a Custom Pattern Checker
3.7.4.2.4. Add the PRBS Pattern Checker
3.7.4.2.5. Add a One-to-Two Streaming Demultiplexer
3.7.4.2.6. Verify the Memory Address Map
3.7.4.1.7. Connect the Reset Signals
3.7.4.1.8. Save the System
3.7.5. Assemble a Hierarchical System
3.7.5.1. Create the Hierarchical Memory Tester System
3.7.5.1.1. Add the Pattern Generator
3.7.5.1.2. Add the Pattern Checker
3.7.5.1.3. Add Memory Master Components
3.7.5.1.3.1. Add a Pattern Writer Component
3.7.5.1.3.2. Add a Pattern Reader Component
3.7.5.1.3.3. Add a RAM Test Controller
3.7.4.1.7. Connect the Reset Signals
3.7.5.1.5. Verify the Memory Address Map
3.7.4.1.8. Save the System
3.7.5.2. Complete the Top-Level System
3.7.6. Viewing the Memory Tester System in Platform Designer
3.7.7. Compiling and Downloading Software to a Development Board
3.7.8. Debugging Your Design
3.7.9. Verifying Hardware in System Console
3.7.9.1. Open the Tutorial Project
3.7.9.2. Add the JTAG-to- Avalon Master Bridge
3.7.9.3. Debug with System Console
3.7.10. Simulating Custom Components
3.7.10.1. Generate a Testbench System in Platform Designer
3.7.10.1.1. Create a New Platform Designer System for the Design Under Test
3.7.10.1.2. Export Design Under Test
3.7.10.1.3. Generate a Testbench System
3.7.10.1.4. Generate Testbench System's Simulation Models
3.7.10.2. Run Simulation In the ModelSim Software
3.7.10.2.1. Set Up the Simulation Environment
3.7.10.2.2. Run the Simulation
3.7.11. View a Diagram of the Completed System
3.8. Hardware System Design with Intel Quartus Prime and Platform Designer Revision History
4. Software System Design with a Nios II Processor
4.1. Nios II Command-Line Tools
4.1.1. Intel Command-Line Tools for Board Bringup and Diagnostics
4.1.1.1. jtagconfig
4.1.1.1.1. jtagconfig Usage Example
4.1.1.2. nios2-configure-sof
4.1.1.2.1. nios2-configure-sof Usage Example
4.1.1.3. system-console
4.1.2. Intel Command-Line Tools for Flash Programming
4.1.2.1. nios2-flash-programmer
4.1.2.1.1. nios2-flash-programmer Usage Example
4.1.2.2. elf2flash, bin2flash, and sof2flash
4.1.2.2.1. bin2flash Usage Example
4.1.3. Intel Command-Line Tools for Software Development and Debug
4.1.3.1. nios2-terminal
4.1.3.2. nios2-download
4.1.3.2.1. nios2-download Usage Example
4.1.3.3. nios2-stackreport
4.1.3.3.1. nios2-stackreport Usage Example
4.1.3.4. validate_zip
4.1.3.4.1. validate_zip Usage Example
4.1.3.5. nios2-gdb-server
4.1.3.5.1. nios2-gdb-server Usage Example
4.1.4. Intel Command-Line Nios II Software Build Tools
4.1.4.1. BSP Related Tools
4.1.4.2. Application Related Tools
4.1.5. Rebuilding Software from the Command Line
4.1.6. GNU Command-Line Tools
4.1.6.1. nios2-elf-addr2line
4.1.6.1.1. nios2-elf-addr2line Usage Example
4.1.6.2. nios2-elf-gdb
4.1.6.3. nios2-elf-readelf
4.1.6.3.1. nios2-elf-readelf Usage Example
4.1.6.4. nios2-elf-ar
4.1.6.4.1. nios2-elf-ar Usage Example
4.1.6.5. Linker
4.1.6.5.1. Linker Usage Example
4.1.6.6. nios2-elf-size
4.1.6.6.1. nios2-elf-size Usage Example
4.1.6.7. nios2-elf-strings
4.1.6.7.1. nios2-elf-strings Usage Example
4.1.6.8. nios2-elf-strip
4.1.6.8.1. nios2-elf-strip Usage Example
4.1.6.8.2. nios2-elf-strip Usage Notes
4.1.6.9. nios2-elf-gdbtui
4.1.6.10. nios2-elf-gprof
4.1.6.11. nios2-elf-gcc and g++
4.1.6.11.1. Compilation Command Usage Example
4.1.6.11.2. More Complex Compilation Example
4.1.6.12. nios2-elf-c++filt
4.1.6.12.1. nios2-elf-c++filt Usage Example
4.1.6.12.2. More Complex nios2-elf-c++filt Example
4.1.6.13. nios2-elf-nm
4.1.6.13.1. nios2-elf-nm Usage Example
4.1.6.13.2. More Complex nios2-elf-nm Example
4.1.6.14. nios2-elf-objcopy
4.1.6.14.1. nios2-elf-objcopy Usage Example
4.1.6.15. nios2-elf-objdump
4.1.6.15.1. nios2-elf-objdump Usage Description
4.1.6.16. nios2-elf-ranlib
4.2. Developing Nios II Software
4.2.1. Software Development Cycle
4.2.1.1. Nios II Software Design
4.2.1.1.1. Nios II Tools Overview
4.2.1.1.2. Nios II Software Build Tools
4.2.1.2. Nios II Software Development Process
4.2.2. Software Project Mechanics
4.2.2.1. Software Tools Background
4.2.2.2. Development Flow Guidelines
4.2.2.3. Nios II Software Build Tools
4.2.2.3.1. The Nios II Software Build Tools for Eclipse
4.2.2.3.2. The Nios II Software Build Tools Command Line
4.2.2.4. Configuring BSP and Application Projects
4.2.2.4.1. Software Example Designs
4.2.2.4.2. Selecting the Operating System (HAL versus MicroC/OS-II RTOS)
4.2.2.4.3. Configuring the BSP Project
4.2.2.4.3.1. MicroC/OS-II RTOS Configuration Tips
4.2.2.4.3.2. HAL Configuration Tips
4.2.2.4.3.3. Adding Software Packages
4.2.2.4.3.4. Using Tcl Scripts with the Nios II BSP Editor
4.2.2.4.3.5. Exporting a Tcl Script
4.2.2.4.3.6. Importing a Tcl Script to Create a New BSP
4.2.2.4.4. Configuring the Application Project
4.2.2.4.4.1. Application Configuration Tips
4.2.2.4.4.2. Linking User Libraries
4.2.2.4.5. Makefiles and the Nios II Software Build Tools for Eclipse
4.2.2.4.6. Building and Running the Software in Nios II Software Build Tools for Eclipse
4.2.2.4.6.1. Building the Project
4.2.2.4.6.2. Downloading and Running the Software
4.2.2.4.6.3. Communicating with the Target
4.2.2.4.6.4. Software Debugging in Nios II Software Build Tools for Eclipse
4.2.2.4.6.5. Run Time Stack Checking
4.2.2.5. Ensuring Software Project Coherency
4.2.2.5.1. Recommended Development Practice
4.2.2.5.2. Recommended Architecture Practice
4.2.3. Developing With the Hardware Abstraction Layer
4.2.3.1. Overview of the HAL
4.2.3.1.1. HAL Configuration Options
4.2.3.1.2. Configuring the Boot Environment
4.2.3.1.3. Controlling HAL Initialization
4.2.3.1.4. Minimizing the Code Footprint and Increasing Performance
4.2.3.1.5. Configuring Peripherals and Services
4.2.3.2. System Startup in HAL-Based Applications
4.2.3.2.1. System Initialization
4.2.3.2.2. crt0 Initialization
4.2.3.2.3. HAL Initialization
4.2.3.3. HAL Peripheral Services
4.2.3.3.1. Timers
4.2.3.3.1.1. System Clock Timer
4.2.3.3.1.2. Timestamp Timer
4.2.3.3.2. Character Mode Devices
4.2.3.3.2.1. stdin, stdout, and stderr
4.2.3.3.2.2. Blocking versus Non-Blocking I/O
4.2.3.3.2.3. Adding Your Own Character Mode Device
4.2.3.3.3. Flash Memory Devices
4.2.3.3.3.1. Memory Initialization, Querying, and Device Support
4.2.3.3.3.2. Accessing the Flash Memory
4.2.3.3.3.3. Configuration and Use Limitations
4.2.3.3.4. Direct Memory Access Devices
4.2.3.3.4.1. DMA Configuration and Use Model
4.2.3.3.4.2. RX-Only DMA Component
4.2.3.3.4.3. TX-Only DMA Component
4.2.3.3.4.4. RX and TX DMA Component
4.2.3.3.4.5. DMA Data-Width Parameter
4.2.3.3.4.6. Configuration and Use Limitations
4.2.3.3.5. Files and File Systems
4.2.3.3.5.1. The Host-Based File System
4.2.3.3.5.2. Read-Only Zip File System
4.2.3.3.6. Unsupported Devices
4.2.3.4. Accessing Memory With the Nios II Processor
4.2.3.4.1. Creating General C/C++ Applications
4.2.3.4.2. Accessing Peripherals
4.2.3.4.3. Sharing Uncached Memory
4.2.3.4.4. Sharing Memory With Cache Performance Benefits
4.2.3.5. Handling Exceptions
4.2.3.6. Modifying the Exception Handler
4.2.4. Linking Applications
4.2.4.1. Background
4.2.4.2. Linker Sections and Application Configuration
4.2.4.3. HAL Linking Behavior
4.2.4.3.1. Default BSP Linking
4.2.4.3.2. User-Controlled BSP Linking
4.3. Nios II MPU Usage
4.3.1. Requirements
4.3.2. General Usage
4.3.2.1. Adding the MPU Hardware
4.3.2.2. Writing Software for the MPU
4.3.2.2.1. MPU Programming Guidelines
4.3.2.2.2. Operating Systems and the MPU
4.3.2.2.3. MPU Register Details
4.3.2.2.3.1. Register mpubase Usage
4.3.2.2.3.2. Register mpuacc Usage
4.3.2.2.3.3. Defining Regions with mpubase and mpuacc
4.3.2.2.4. Flow Summary
4.3.3. Nios II MPU Design Examples
4.3.3.1. Working with the MPU Design Examples
4.3.3.2. Example Hardware
4.3.3.3. Region Layout Considerations
4.3.3.4. Software
4.3.3.4.1. MPU Utilities
4.3.3.4.2. Building the Software
4.3.3.4.2.1. mpu_exc_detection Console Output
4.4. Profiling Nios II Systems
4.4.1. Requirements
4.4.1.1. Obtaining the Hardware Design
4.4.1.2. Obtaining the Software Examples
4.4.2. Tools
4.4.2.1. GNU Profiler
4.4.2.2. Intel Performance Counter
4.4.2.3. High-Resolution Timer
4.4.2.4. Program Counter Trace Information
4.4.3. Using the GNU Profiler to Measure Code Performance
4.4.3.1. GNU Profiler Advantages
4.4.3.2. GNU Profiler Limitations
4.4.3.3. Software Considerations
4.4.3.3.1. Profiler Mechanics
4.4.3.3.2. Profiler Overhead
4.4.3.3.2.1. Memory
4.4.3.3.2.2. Processor Cycles
4.4.3.4. Hardware Considerations
4.4.3.5. Tutorial: Using the GNU Profiler
4.4.3.5.1. Profiler Example with the Nios II Command Line
4.4.3.5.1.1. Creating the Profiler Software Example
4.4.3.5.1.2. Running the Profiler Software Example
4.4.3.5.1.3. Creating the GNU Profiler Report
4.4.3.5.2. Profiler Example with Nios II SBT for Eclipse
4.4.3.5.2.1. Creating and Running the Profiler Software Example
4.4.3.5.2.2. Viewing the GNU Profiler Report
4.4.3.5.3. Analyzing the GNU Profiler Report
4.4.4. Using Performance Counter and Timer Components
4.4.4.1. Performance Counter Advantages
4.4.4.2. Timer Advantages
4.4.4.3. Performance Counter and Timer Hardware Considerations
4.4.4.4. Performance Counter and Timer Software Considerations
4.4.4.5. Performance Counter Software Considerations
4.4.4.6. The Global Counter
4.4.4.7. Hardware Considerations
4.4.4.8. Tutorial: Using Performance Counters and Timers
4.4.4.8.1. Modifying the Nios II Hardware Design
4.4.4.8.2. Programming the Hardware Design to Your Device
4.4.4.8.3. Performance Counter Example with the Nios II Command Line
4.4.4.8.3.1. Creating the Performance Counter Software Example
4.4.4.8.3.2. Running the Performance Counter Software Example
4.4.4.8.4. Performance Counter Example with Nios II SBT for Eclipse
4.4.4.8.5. Analyzing the Performance Counter Report
4.4.5. Troubleshooting
4.4.5.1. nios2-elf-gprof –annotated-source Switch Has No Effect
4.4.5.2. Writing to the Registers of a Nonexistent Section Counter
4.4.5.3. Output From a printf() or perf_print_formatted_output() Call Near the End
4.4.5.4. Fitting a Performance Counter in a Hardware Design That Consumes Most
4.4.5.5. The Histogram for the gmon.out File Is Missing, Even Though My main()
4.5. Software System Design with a Nios II Processor Revision History
5. Nios II Configuration and Booting Solutions
5.1. Introduction
5.1.1. Prerequisites
5.2. Nios II Processor Booting Methods
5.2.1. Introduction to Nios II Booting Methods
5.2.1.1. Nios II Processor Application Execute-In-Place from Boot Flash
5.2.1.1.1. alt_load ()
5.2.1.2. Nios II Processor Application Copied from Boot Flash to RAM Using Boot Copier
5.2.1.2.1. Memcpy-based Boot Copier
5.2.1.3. Nios II Processor Application Execute-In-Place from OCRAM
5.2.2. Nios II Processor Booting from On-Chip Flash (UFM)
5.2.2.1. Intel MAX 10 FPGA On-Chip Flash Description
5.2.2.2. Nios II Processor Application Execute-In-Place from UFM
5.2.2.2.1. Hardware Design
5.2.2.2.2. Application
5.2.2.2.3. Programming
5.2.2.3. Nios II Processor Application Copied from UFM to RAM using Boot Copier
5.2.2.3.1. Hardware Design
5.2.2.3.2. Application
5.2.2.3.3. Programming
5.2.3. Nios II Processor Booting from EPCQ Flash
5.2.3.1. Intel FPGA Serial Flash Controller (EPCQ) Overview
5.2.3.2. Nios II Processor Design, Configuration, and Boot Flow
5.2.3.3. Nios II Processor Application Execute-In-Place from EPCQ Flash
5.2.3.3.1. Hardware Design
5.2.3.3.2. Application
5.2.3.3.3. Programming
5.2.3.4. Nios II Processor Application Copied from EPCQ Flash to RAM Using Boot Copier
5.2.3.4.1. Hardware Design
5.2.3.4.2. Application
5.2.3.4.3. Programming
5.2.3.5. EPCQ HAL Driver
5.2.4. Nios II Processor Booting from QSPI Flash
5.2.4.1. Nios II Processor Design, Configuration and Boot Flow
5.2.4.2. Nios II Processor Application Executes In-Place from General Purpose QSPI Flash ( Intel MAX 10)
5.2.4.2.1. Hardware Design
5.2.4.2.2. Application
5.2.4.2.3. Programming Files Generation
5.2.4.2.4. QSPI Flash Programming
5.2.4.3. Nios II Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier ( Intel MAX 10)
5.2.4.3.1. Hardware Design
5.2.4.3.2. Application
5.2.4.3.3. Programming Files Generation
5.2.4.3.4. QSPI Flash Programming
5.2.4.4. Nios II Processor Application Executes In-Place from Configuration QSPI Flash (Other FPGA devices)
5.2.4.4.1. Hardware Design
5.2.4.4.2. Application
5.2.4.4.3. Programming Files Generation
5.2.4.4.4. QSPI Flash Programming
5.2.4.5. Nios II Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Other FPGA devices)
5.2.4.5.1. Hardware Design
5.2.4.5.2. Application
5.2.4.5.3. Programming Files Generation
5.2.4.5.4. QSPI Flash Programming
5.2.5. Nios II Processor Booting from On-Chip Memory (OCRAM)
5.2.5.1. Nios II Processor Application Executes in-place from OCRAM
5.2.5.1.1. Hardware Design
5.2.5.1.2. Application
5.2.5.1.3. Programming
5.2.6. Nios II Processor Booting from CFI Flash
5.2.6.1. Description of the Avalon Tri-State Conduit Components
5.2.6.2. Nios II Processor Application Execute-In-Place from CFI Flash
5.2.6.2.1. Hardware Design
5.2.6.2.2. Application
5.2.6.2.3. Programming
5.2.6.3. Nios II Processor Application Copied from CFI Flash to RAM using Boot Copier
5.2.6.3.1. Hardware Design
5.2.6.3.2. Application
5.2.6.3.3. Programming
5.2.7. Summary of Nios II Processor Vector Configurations and BSP Settings
5.3. Alternative Nios II Boot Methods
5.3.1. Assumptions About the Reader
5.3.2. Implementing a Custom Boot Copier
5.3.2.1. Hardware Design Files
5.3.2.2. Software Files
5.3.3. Default Nios II Boot Copier
5.3.3.1. Overview of the Default Nios II Boot Copier
5.3.3.2. The Default CFI Flash Boot Copier
5.3.3.3. The Default EPCS/EPCQ Boot Copier
5.3.4. Advanced Boot Copier Example
5.3.4.1. Driver Initialization
5.3.4.2. Printing to the JTAG UART
5.3.4.2.1. Preventing Stalls by the JTAG UART
5.3.4.2.2. Reducing Memory Use for Printing
5.3.4.3. Boot Images
5.3.4.3.1. Boot Image Format
5.3.4.3.2. Boot Image Header Format
5.3.4.3.3. Boot Record Format
5.3.4.3.4. Choosing a Boot Image
5.3.4.3.5. Word Alignment
5.3.4.4. Boot Methods
5.3.4.4.1. Booting Directly From CFI Flash
5.3.4.4.2. Booting From CFI Flash, Running From On-Chip Memory
5.3.4.4.3. Booting From EPCS/EPCQ Flash, Running From On-Chip Memory
5.3.4.4.4. Setting the Boot Method
5.3.4.5. Preventing Overlapping Data in Flash
5.3.4.5.1. Overlapping Data in CFI Flash
5.3.4.5.2. Overlapping Data in EPCS/EPCQ Flash
5.3.4.6. Boot Copier Code Size
5.3.5. Implementing the Advanced Boot Copier Example
5.3.5.1. Setting Up the Software Tools and Development Board
5.3.5.2. Creating a Suitable Hardware Design
5.3.5.2.1. Opening the Example Project
5.3.5.2.2. Adding On-chip Boot ROM to the System
5.3.5.3. Building the Advanced Boot Copier
5.3.5.4. Building a Test Application to Boot
5.3.5.5. Packing the Test Application in a Boot Record
5.3.5.6. Booting Directly From CFI Flash Memory
5.3.5.7. Booting CFI or EPCS/EPCQ Flash From On-Chip Memory
5.3.5.8. Running the Advanced Boot Copier Example
5.3.6. Small Boot Copier Example
5.3.6.1. Small Boot Copier Features
5.3.6.2. Implementation in Nios II Assembly Language
5.3.6.3. System Initialization
5.3.6.4. Code Size
5.3.7. Implementing the Small Boot Copier Example
5.3.7.1. Setting Up the Software Tools and Development Board
5.3.7.2. Creating a Suitable Hardware Design
5.3.7.3. Building the Small Boot Copier Using 'make'
5.3.5.4. Building a Test Application to Boot
5.3.7.5. Booting From On-Chip Memory
5.3.7.6. Running the Small Boot Copier Example
5.3.8. Debugging Boot Copiers
5.3.8.1. Hardware and Software Breakpoints
5.3.8.2. Enabling Hardware Breakpoints
5.3.8.3. Breaking Before main()
5.3.8.4. Setting Up the Debugger
5.3.9. Externally Controlling the Nios II Boot Process
5.3.9.1. Overview
5.3.9.2. Building an Appropriate Platform Designer System
5.3.9.2.1. External Processor Bridge
5.3.9.2.2. The cpu_resetrequest Signal
5.3.9.2.3. Nios II Reset Address
5.3.9.2.4. One-Bit PIO Peripheral
5.3.9.3. The Boot Process
5.3.9.3.1. Boot Images
5.3.9.3.2. Example C Code
5.3.9.3.3. External Boot Flow
5.4. Boot Time Performance Analysis
5.4.1. Boot Time Performance Analysis Design Example
5.4.2. Boot Time Measurement Strategy
5.4.3. Reducing Nios II Boot Time in Intel MAX 10 FPGA Design
5.4.3.1. Boot Methods
5.4.3.2. Boot Device Performance
5.4.3.3. Peripheral Initialization
5.4.3.4. Nios II Processor Caches
5.4.3.5. System Speed
5.4.3.6. Intel MAX 10 FPGA Nios II Flash Accelerator
5.4.4. Boot Time Performance and Estimation
5.4.4.1. Boot Time Performance for Design that Boots from On Chip Flash with Flash Accelerator
5.4.4.2. Boot Time Estimation
5.5. Nios II Configuration and Booting Solutions Revision History
6. Nios II Debug, Verification, and Simulation
6.1. Software Debugging Options
6.2. Debugging Nios II Designs
6.2.1. Debuggers
6.2.1.1. Nios II Software Development Tools
6.2.1.1.1. Nios II System ID
6.2.1.1.2. Project Templates
6.2.1.1.3. Configuration Options
6.2.1.1.3.1. Objdump File
6.2.1.1.3.2. Show Make Commands
6.2.1.1.3.3. Show Line Numbers
6.2.1.1.4. Nios II GDB Console and GDB Commands
6.2.1.1.5. Nios II Console View and stdio Library Functions
6.2.1.1.6. Importing Projects Created Using the Nios II Software Build Tools
6.2.1.1.7. Selecting a Processor Instance in a Multiple Processor Design
6.2.1.2. Signal Tap II Embedded Logic Analyzer
6.2.1.3. Lauterbach Trace32 Debugger and PowerTrace Hardware
6.2.1.4. Data Display Debuggers
6.2.2. Run-Time Analysis Debug Techniques
6.2.2.1. Software Profiling
6.2.2.2. Watchpoints
6.2.2.3. Stack Overflow
6.2.2.3.1. Enabling Run Time Stack Checking
6.2.2.4. Hardware Abstraction Layer (HAL)
6.2.2.5. Breakpoints
6.2.2.6. Debugger Stepping and Using No Optimizations
6.2.3. Using the Debug Code from Intel MAX 10 On-Chip Flash - User Flash Memory (UFM)
6.2.3.1. Building Hardware Design in Platform Designer (Standard)
6.2.3.2. Compiling using the Intel Quartus Prime
6.2.3.3. Building Software Design
6.2.3.4. Creating the POF File
6.2.3.5. Programming the POF File
6.2.3.6. Debugging the Nios II Software Running in On-Chip Flash
6.3. Verification and Board Bring-Up
6.3.1. Verification Methods
6.3.1.1. Prerequisites
6.3.1.2. System Console
6.3.1.3. Signal Tap II Embedded Logic Analyzer
6.3.1.4. External Instrumentation
6.3.1.4.1. Signal Probe Signal Probe
6.3.1.4.2. Logic Analyzer Interface
6.3.1.5. Stimuli Generation
6.3.2. Board Bring-up
6.3.2.1. Peripheral Testing
6.3.2.1.1. Data Trace Failure
6.3.2.1.2. Address Trace Failure
6.3.2.1.3. Device Isolation
6.3.2.1.4. JTAG
6.3.2.2. Board Testing
6.3.2.3. Minimal Test System
6.3.3. System Verification
6.3.3.1. Designing with Verification in Mind
6.3.3.2. Accelerating Verification
6.3.3.3. Using Software to Verify Hardware
6.3.3.4. Environmental Testing
6.4. Additional Embedded Design Considerations
6.4.1. JTAG Signal Integrity
6.4.2. Memory Space For System Prototyping
6.5. Simulating Nios II Embedded Processor Designs
6.5.1. Before You Begin
6.5.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.5.2.1. Platform Designer-Generated System Simulation Files
6.5.2.2. Memory Simulation Models
6.5.2.3. Using IP and Platform Designer Simulation Setup Scripts
6.5.3. Creating the Nios II Software
6.5.3.1. Creating a Software Project Using Nios II SBT for Eclipse
6.5.3.2. Creating a Software Project Using Command Line
6.5.4. Running Simulation in the ModelSim Simulator Using Nios II SBT for Eclipse
6.5.5. Running Simulation in the ModelSim Simulator Using Command Line
6.6. Nios II Debug, Verification, and Simulation Revision History
7. Optimizing Nios II Based Systems and Software
7.1. Hardware Acceleration and Coprocessing
7.1.1. Hardware Acceleration
7.1.1.1. Customizing and Accelerating FPGA Designs
7.1.1.2. Accelerating Cyclic Redundancy Checking (CRC)
7.1.1.2.1. Matching I/O Bandwidths
7.1.1.2.2. Pipelining Algorithms
7.1.1.3. Creating Nios II Custom Instructions
7.1.2. Coprocessing
7.1.2.1. Creating Multicore Designs
7.1.2.1.1. Accessing Multiple Nios II Designs
7.1.2.2. Pre- and Post-Processing
7.1.2.3. Replacing State Machines
7.1.2.3.1. Low-Speed State Machines
7.1.2.3.2. High-Speed State Machines
7.1.2.3.3. Subdivided State Machines
7.2. Software Application Optimization
7.2.1. Performance Tuning Background
7.2.2. Speeding Up System Processing Tasks
7.2.2.1. Analyzing the Problem
7.2.2.2. Accelerating your Application
7.2.2.2.1. Increasing Processor Efficiency
7.2.2.2.2. Accelerating Hardware
7.2.2.2.3. Improving Data Movement
7.2.3. Accelerating Interrupt Service Routines
7.2.3.1. Analyzing the Problem
7.2.3.2. Accelerating the Interrupt Service Routine
7.2.4. Reducing Code Size
7.2.4.1. Analyzing the Problem
7.2.4.2. Reducing the Code Footprint
7.3. Memory Optimization
7.3.1. Isolate Critical Memory Connections
7.3.2. Match Master and Slave Data Width
7.3.3. Use Separate Memories to Exploit Concurrency
7.3.4. Understand the Nios II Instruction Master Address Space
7.3.5. Test Memory
7.4. Accelerating Nios II Networking Applications
7.4.1. Downloading the Ethernet Acceleration Design Example
7.4.2. The Structure of Networking Applications
7.4.2.1. Ethernet System Hierarchy
7.4.2.2. Relationships Between Networking System Elements
7.4.2.3. Finding the Performance Bottlenecks
7.4.3. The User Application
7.4.3.1. User Application Optimizations
7.4.3.1.1. Software Optimizations
7.4.3.1.2. Hardware Optimizations
7.4.3.1.3. The Sockets API
7.4.3.1.3.1. Selecting the Right Networking Protocol
7.4.3.1.3.2. Improving Send and Receive Performance
7.4.3.1.3.3. The Zero Copy API
7.4.4. Structure of the NicheStack Networking Stack
7.4.4.1. General Optimizations
7.4.4.2. NicheStack Specific Optimizations
7.4.4.2.1. NicheStack Thread Priorities
7.4.4.2.2. Disabling Nonessential NicheStack Modules
7.4.4.2.3. Using Faster Packet Memory
7.4.4.2.3.1. Background
7.4.4.2.3.2. Solution
7.4.4.2.4. Super Loop Mode
7.4.4.2.5. NicheStack Support and Licensing
7.4.5. Ethernet Device
7.4.5.1. Link Speed
7.4.5.2. Network Interface (Intel FPGA Triple Speed Ethernet Intel FPGA IP Function)
7.4.5.3. NicheStack Device Driver Model
7.4.6. Benchmarking Setup, Results, and Analysis
7.4.6.1. Overview
7.4.6.2. Test Setup
7.4.6.2.1. Test Systems
7.4.6.3. Test Methodology
7.4.6.3.1. Ethernet Link Type
7.4.6.3.2. Protocols Tested
7.4.6.3.3. Data Transmission Sizes
7.4.6.3.4. Test Runs
7.4.6.4. Nios II System Software Configuration
7.4.6.4.1. NicheStack Networking Stack Configuration
7.4.6.4.2. MicroC/OS-II Configuration
7.4.6.4.3. Benchmark Application
7.4.6.4.4. General Application and System Library Settings
7.4.6.5. Workstation System Software
7.4.7. Nios II Test Hardware and Test Results
7.5. Using Tightly Coupled Memory with the Nios II Processor Tutorial
7.5.1. Reasons for Using Tightly Coupled Memory
7.5.2. Tradeoffs
7.5.3. Guidelines for Using Tightly Coupled Memory
7.5.3.1. Hardware Guidelines
7.5.3.2. Software Guidelines
7.5.3.2.1. Locating Functions in Tightly Coupled Memory
7.5.4. Tightly Coupled Memory Interface
7.5.4.1. Restrictions
7.5.4.2. Dual Port Memories
7.5.5. Building a Nios II System with Tightly Coupled Memory
7.5.5.1. Hardware and Software Requirements
7.5.5.2. Modify the Example Design to Include Tightly Coupled Memories
7.5.5.3. Create the Tightly Coupled Memories
7.5.5.4. Connect and Position the Tightly Coupled Memories
7.5.5.5. Add a Performance Counter
7.5.6. Generate the Platform Designer System
7.5.7. Run the Tightly Coupled Memories Examples from the Nios II Command
7.5.8. Program and Run the Tightly Coupled Memory Project
7.5.9. Understanding the Tcl Scripts
7.5.9.1. Timer Memory
7.5.9.2. Exception Stack
7.5.9.3. Timer Definitions
7.5.9.3.1. peripheral_subsystem_sys_clk_timer
7.5.9.3.2. peripheral_subsystem_high_res_timer
7.6. Optimizing Nios II Based Systems and Software Revision History