Arria 10 Avalon Streaming with SR-IOV IP for PCIe User Guide - Arria 10 PCIe IP using Avalon-ST with SR-IOV, multi-function support - 2024-09-12

Version: 20.4

1. Datasheet
1.1. Arria 10 Avalon -ST Interface with SR-IOV for PCI Express Datasheet
1.1.1. SR-IOV Features
1.2. Release Information
1.3. Device Family Support
1.4. Debug Features
1.5. IP Core Verification
1.5.1. Compatibility Testing Environment
1.6. Performance and Resource Utilization
1.7. Recommended Speed Grades for SR-IOV Interface
2. Getting Started with the SR-IOV Design Example
2.1. Directory Structure for Arria 10 SR-IOV Design Example
2.2. Design Components for the SR-IOV Design Example
2.3. Generating the SR-IOV Design Example
2.4. Compiling and Simulating the Design for SR-IOV
3. Parameter Settings
3.1. Parameters
3.2. Arria 10 Avalon-ST Settings
3.3. Arria 10 SR-IOV System Settings
3.4. Base Address Register (BAR) Settings
3.5. SR-IOV Device Identification Registers
3.6. Arria 10 Interrupt Capabilities
3.7. Physical Function TLP Processing Hints (TPH)
3.8. Address Translation Services (ATS)
3.9. PCI Express and PCI Capabilities Parameters
3.9.1. PCI Express and PCI Capabilities
3.9.2. Error Reporting
3.9.3. Link Capabilities
3.9.4. Slot Capabilities
3.9.5. Power Management
3.10. PHY Characteristics
3.11. Example Designs
4. Physical Layout
4.1. Hard IP Block Placement In Cyclone 10 GX Devices
4.2. Hard IP Block Placement In Arria 10 Devices
4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions
5.1. Avalon-ST TX Interface
5.2. Component-Specific Avalon-ST Interface Signals
5.3. Avalon-ST RX Interface
5.4. BAR Hit Signals
5.5. Configuration Status Interface
5.6. Clock Signals
5.7. Function-Level Reset (FLR) Interface
5.8. SR-IOV Interrupt Interface
5.9. Configuration Extension Bus (CEB) Interface
5.9.1. Vital Product Data (VPD) Capability
5.9.1.1. Determine the Pointer Address of an External Capability Register
5.9.1.2. VPD Capability Implementation
5.10. Implementing MSI-X Interrupts
5.11. Control Shadow Interface
5.12. Local Management Interface (LMI) Signals
5.13. Reset, Status, and Link Training Signals
5.14. Hard IP Reconfiguration Interface
5.15. Serial Data Signals
5.16. Test Signals
5.17. PIPE Interface Signals
5.18. Arria 10 Development Kit Conduit Interface
6. Registers
6.1. Addresses for Physical and Virtual Functions
6.2. Correspondence between Configuration Space Registers and the PCIe Specification
6.3. PCI and PCI Express Configuration Space Registers
6.3.1. Type 0 Configuration Space Registers
6.3.2. PCI and PCI Express Configuration Space Register Content
6.3.3. Interrupt Line and Interrupt Pin Register
6.4. MSI Registers
6.5. MSI-X Capability Structure
6.6. Power Management Capability Structure
6.7. PCI Express Capability Structure
6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register
6.9. Uncorrectable Error Status Register
6.10. Uncorrectable Error Mask Register
6.11. Uncorrectable Error Severity Register
6.12. Correctable Error Status Register
6.13. Correctable Error Mask Register
6.14. Advanced Error Capabilities and Control Register
6.15. Header Log Registers 0-3
6.16. SR-IOV Virtualization Extended Capabilities Registers
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map
6.16.2. ARI Enhanced Capability Header
6.16.3. SR-IOV Enhanced Capability Registers
6.16.4. Initial VFs and Total VFs Registers
6.16.5. VF Device ID Register
6.16.6. Page Size Registers
6.16.7. VF Base Address Registers (BARs) 0-5
6.16.8. Secondary PCI Express Extended Capability Header
6.16.9. Lane Status Registers
6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
6.17. Virtual Function Registers
7. Reset and Clocks
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
7.2. Function Level Reset (FLR)
7.3. Clocks
7.3.1. Clock Domains
7.3.1.1. coreclkout_hip
7.3.1.2. pld_clk
7.3.2. Clock Summary
8. Programming and Testing SR-IOV Bridge MSI Interrupts
8.1. Setting Up and Verifying MSI Interrupts
8.2. Masking MSI Interrupts
8.3. Dropping a Pending MSI Interrupt
9. Error Handling
9.1. Physical Layer Errors
9.2. Data Link Layer Errors
9.3. Transaction Layer Errors
9.4. Error Reporting and Data Poisoning
9.5. Uncorrectable and Correctable Error Status Bits
10. IP Core Architecture
10.1. PCI Express Protocol Stack
10.2. Data Link Layer
10.3. Physical Layer
10.4. Top-Level Interfaces
10.4.1. Avalon-ST Interface
10.4.2. Clocks and Reset
10.4.3. Interrupts
10.4.4. PIPE
10.5. Arria 10 Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
11. Design Implementation
11.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins
11.2. Recommended Reset Sequence to Avoid Link Training Issues
11.3. SDC Timing Constraints
12. Debugging
12.1. Setting Up Simulation
12.1.1. Changing Between Serial and PIPE Simulation
12.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants
12.1.3. Viewing the Important PIPE Interface Signals
12.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
12.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
12.2. Simulation Fails To Progress Beyond Polling.Active State
12.3. Hardware Bring-Up Issues
12.4. Link Training
12.5. Creating a Signal Tap Debug File to Match Your Design Hierarchy
12.6. Use Third-Party PCIe Analyzer
12.7. BIOS Enumeration Issues
13. Document Revision History
13.1. Document Revision History for the Arria 10 Avalon Streaming with SR-IOV IP for PCIe User Guide
A. Transaction Layer Packet (TLP) Header Formats
A.1. TLP Packet Formats without Data Payload
A.2. TLP Packet Formats with Data Payload
B. Arria 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive

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