| TX Interface |
|
ctr64_axc_tx_ready[N]
|
8 |
Input |
Each asserted bit indicates the CPRI mapper
is ready to read Ctrl_Axc data from the corresponding byte of
ctrl_axc_tx_data on the
next clock cycle. |
|
ctrl64_axc_tx_valid[N]
|
8 |
Output |
Write valid for ctrl_axc_tx_data. Assert bit [n] to indicate that
the corresponding byte on the current ctrl_axc_tx_data bus is valid Ctrl_AxC
data. |
|
ctrl64_axc_tx_data[N]
|
64 |
Output |
Ctrl_AxC data to be written to the CPRI
frame. The CPRI mapper writes the individual bytes of the
current value on the ctrl_axc_tx_data bus to the CPRI frame based on
the ctrl_axc_tx_ready signal
from the previous cycle, and the ctrl_axc_tx_valid signal in the current
cycle. |
| RX Interface |
|
ctrl64_axc_rx_valid[N]
|
4 |
Input |
Assertion of the bit indicates the
corresponding byte on the current ctrl64_axc_rx_data bus is valid Ctrl_AxC
data. |
|
ctrl64_axc_rx_data[N]
|
64 |
Input |
IQ data received from the CPRI frame. The
ctrl64_axc_rx_valid signal
indicates valid Ctrl AxC data bytes. |