| TX Interface |
|
ctrl32_axc_tx_ready[N]
|
4 |
Input |
Assertion of the bits indicate the CPRI mapper is
ready to read Ctrl_AxC data from the corresponding byte of ctrl_axc_tx_data on the next clock
cycle. |
|
ctrl32_axc_tx_valid[N]
|
4 |
Output |
Write valid for ctrl_axc_tx_data. Assert bit [n] to indicate that the
corresponding byte on the current ctrl_axc_tx_data bus is valid Ctrl_AxC data. |
|
ctrl32_axc_tx_data[N]
|
64 |
Output |
Ctrl_AxC data to be written to the CPRI frame.
The CPRI mapper writes the individual bytes of the current value on
the ctrl_axc_tx_data bus to the
CPRI frame based on the ctrl_axc_tx_ready signal from the previous cycle, and
the ctrl_axc_tx_valid signal in the
current cycle. |
| RX Interface |
|
ctrl32_axc_rx_valid[N]
|
4 |
Input |
Each asserted bit indicates the corresponding
byte on the current ctrl_axc_rx_data bus is valid Ctrl_AxC data. |
|
ctrl32_axc_rx_data[N]
|
64 |
Input |
Ctrl_AxC data received from the CPRI frame. The
ctrl_axc_rx_valid signal
indicates valid Ctrl_AxC data bytes. |