L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide - This IP contains a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express* Base Specification and supports the Avalon® memory-mapped and Avalon® memory-mapped with DMA interfaces to the application in the FPGA core. - 2023-10-02

Version

23.1