External Memory Interfaces Cyclone 10 GX FPGA IP User Guide - The Cyclone 10 GX EMIF IP provides external memory interface support for DDR3 and LPDDR3 memory protocols. - 2024-11-28

Version: 24.1

1. Release Information
2. External Memory Interfaces Cyclone 10 GX FPGA IP Introduction
2.1. Cyclone 10 GX EMIF IP Design Flow
2.2. Cyclone 10 GX EMIF IP Design Checklist
3. Cyclone 10 GX EMIF IP Product Architecture
3.1. EMIF Architecture: Introduction
3.1.1. I/O Subsystem
3.1.2. I/O Column
3.1.3. I/O AUX
3.1.4. I/O Bank
3.1.4.1. Implementing a x8 Interface with Hard Memory Controller
3.1.4.2. Implementing a x72 Interface with Hard Memory Controller
3.1.5. I/O Lane
3.1.6. Input DQS Clock Tree
3.1.7. PHY Clock Tree
3.1.8. PLL Reference Clock Networks
3.1.9. Clock Phase Alignment
3.2. Cyclone 10 GX EMIF Sequencer
3.2.1. DQS Tracking
3.3. Cyclone 10 GX EMIF Calibration
3.3.1. Calibration Stages
3.3.2. Calibration Stages Descriptions
3.3.3. Calibration Algorithms
3.3.4. Calibration Flowchart
3.4. Cyclone 10 GX EMIF Controller
3.4.1. Hard Memory Controller
3.4.1.1. Hard Memory Controller Features
3.4.1.2. Hard Memory Controller Main Control Path
3.4.1.3. Data Buffer Controller
3.4.2. Hard Memory Controller Rate Conversion Feature
3.5. Hardware Resource Sharing Among Multiple EMIFs
3.5.1. I/O Aux Sharing
3.5.2. I/O Bank Sharing
3.5.3. PLL Reference Clock Sharing
3.5.4. Core Clock Network Sharing
3.6. Cyclone 10 GX EMIF Ping Pong PHY
3.6.1. Ping Pong PHY Feature Description
3.6.2. Ping Pong PHY Architecture
3.6.3. Ping Pong PHY Limitations
3.6.4. Ping Pong PHY Calibration
3.6.5. Using the Ping Pong PHY
3.6.6. Ping Pong PHY Simulation Example Design
4. Cyclone 10 GX EMIF IP End-User Signals
4.1. Interface and Signal Descriptions
4.1.1. Intel Cyclone 10 GX EMIF IP Interfaces for DDR3
4.1.1.1. pll_ref_clk for DDR3
4.1.1.2. pll_locked for DDR3
4.1.1.3. pll_extra_clk_0 for DDR3
4.1.1.4. pll_extra_clk_1 for DDR3
4.1.1.5. pll_extra_clk_2 for DDR3
4.1.1.6. pll_extra_clk_3 for DDR3
4.1.1.7. oct for DDR3
4.1.1.8. mem for DDR3
4.1.1.9. status for DDR3
4.1.1.10. afi_reset_n for DDR3
4.1.1.11. afi_clk for DDR3
4.1.1.12. afi_half_clk for DDR3
4.1.1.13. afi for DDR3
4.1.1.14. emif_usr_reset_n for DDR3
4.1.1.15. emif_usr_clk for DDR3
4.1.1.16. emif_usr_reset_n_sec for DDR3
4.1.1.17. emif_usr_clk_sec for DDR3
4.1.1.18. cal_debug_reset_n for DDR3
4.1.1.19. cal_debug_clk for DDR3
4.1.1.20. cal_debug_out_reset_n for DDR3
4.1.1.21. cal_debug_out_clk for DDR3
4.1.1.22. clks_sharing_master_out for DDR3
4.1.1.23. clks_sharing_slave_in for DDR3
4.1.1.24. clks_sharing_slave_out for DDR3
4.1.1.25. ctrl_amm for DDR3
4.1.1.26. ctrl_auto_precharge for DDR3
4.1.1.27. ctrl_user_priority for DDR3
4.1.1.28. ctrl_ecc_user_interrupt for DDR3
4.1.1.29. ctrl_ecc_readdataerror for DDR3
4.1.1.30. ctrl_mmr_slave for DDR3
4.1.1.31. cal_debug for DDR3
4.1.1.32. cal_debug_out for DDR3
4.1.2. Intel Cyclone 10 GX EMIF IP Interfaces for LPDDR3
4.1.2.1. pll_ref_clk for LPDDR3
4.1.2.2. pll_locked for LPDDR3
4.1.2.3. pll_extra_clk_0 for LPDDR3
4.1.2.4. pll_extra_clk_1 for LPDDR3
4.1.2.5. pll_extra_clk_2 for LPDDR3
4.1.2.6. pll_extra_clk_3 for LPDDR3
4.1.2.7. oct for LPDDR3
4.1.2.8. mem for LPDDR3
4.1.2.9. status for LPDDR3
4.1.2.10. afi_reset_n for LPDDR3
4.1.2.11. afi_clk for LPDDR3
4.1.2.12. afi_half_clk for LPDDR3
4.1.2.13. afi for LPDDR3
4.1.2.14. emif_usr_reset_n for LPDDR3
4.1.2.15. emif_usr_clk for LPDDR3
4.1.2.16. cal_debug_reset_n for LPDDR3
4.1.2.17. cal_debug_clk for LPDDR3
4.1.2.18. cal_debug_out_reset_n for LPDDR3
4.1.2.19. cal_debug_out_clk for LPDDR3
4.1.2.20. clks_sharing_master_out for LPDDR3
4.1.2.21. clks_sharing_slave_in for LPDDR3
4.1.2.22. clks_sharing_slave_out for LPDDR3
4.1.2.23. ctrl_user_priority for LPDDR3
4.1.2.24. ctrl_mmr_slave for LPDDR3
4.1.2.25. cal_debug for LPDDR3
4.1.2.26. cal_debug_out for LPDDR3
4.2. AFI Signals
4.2.1. AFI Clock and Reset Signals
4.2.2. AFI Address and Command Signals
4.2.3. AFI Write Data Signals
4.2.4. AFI Read Data Signals
4.2.5. AFI Calibration Status Signals
4.2.6. AFI Shadow Register Management Signals
4.3. AFI 4.0 Timing Diagrams
4.3.1. AFI Address and Command Timing Diagrams
4.3.2. AFI Write Sequence Timing Diagrams
4.3.3. AFI Read Sequence Timing Diagrams
4.3.4. AFI Calibration Status Timing Diagram
4.4. Cyclone 10 GX Memory Mapped Register (MMR) Tables
4.4.1. ctrlcfg0
4.4.2. ctrlcfg1
4.4.3. dramtiming0
4.4.4. sbcfg1
4.4.5. caltiming0
4.4.6. caltiming1
4.4.7. caltiming2
4.4.8. caltiming3
4.4.9. caltiming4
4.4.10. caltiming9
4.4.11. dramaddrw
4.4.12. sideband0
4.4.13. sideband1
4.4.14. sideband2
4.4.15. sideband3
4.4.16. sideband4
4.4.17. sideband5
4.4.18. sideband6
4.4.19. sideband7
4.4.20. sideband8
4.4.21. sideband9
4.4.22. sideband10
4.4.23. sideband11
4.4.24. sideband12
4.4.25. sideband13
4.4.26. dramsts
4.4.27. niosreserve0
4.4.28. niosreserve1
4.4.29. ecc3: ECC Error and Interrupt Configuration
4.4.30. ecc4: Status and Error Information
4.4.31. ecc5: Address of Most Recent SBE/DBE
4.4.32. ecc6: Address of Most Recent Correction Command Dropped
5. Cyclone 10 GX EMIF – Simulating Memory IP
5.1. Simulation Options
5.2. Simulation Walkthrough
5.2.1. Calibration Modes
5.2.2. Abstract PHY Simulation
5.2.3. Simulation Scripts
5.2.4. Functional Simulation with Verilog HDL
5.2.5. Functional Simulation with VHDL
5.2.6. Simulating the Design Example
6. Cyclone 10 GX EMIF IP for DDR3
6.1. Parameter Descriptions
6.1.1. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: General
6.1.2. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Memory
6.1.3. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem I/O
6.1.4. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: FPGA I/O
6.1.5. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Mem Timing
6.1.6. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Board
6.1.7. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Controller
6.1.8. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Diagnostics
6.1.9. Intel Cyclone 10 GX EMIF IP DDR3 Parameters: Example Designs
6.2. Board Skew Equations
6.2.1. Equations for DDR3 Board Skew Parameters
6.3. Pin and Resource Planning
6.3.1. Interface Pins
6.3.1.1. Estimating Pin Requirements
6.3.1.2. DIMM Options
6.3.1.3. Maximum Number of Interfaces
6.3.2. FPGA Resources
6.3.2.1. OCT
6.3.2.2. PLL
6.3.3. Pin Guidelines for Cyclone 10 GX EMIF IP
6.3.3.1. General Guidelines
6.3.3.2. x4 DIMM Implementation
6.3.3.3. Command and Address Signals
6.3.3.4. Clock Signals
6.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.3.6. Resource Sharing Guidelines (Multiple Interfaces)
6.3.3.7. Ping-Pong PHY Implementation
6.4. DDR3 Board Design Guidelines
6.4.1. Terminations and Slew Rates with Cyclone 10 GX Devices
6.4.1.1. Dynamic On-Chip Termination (OCT) in Cyclone 10 Devices
6.4.1.2. Choosing Terminations on Cyclone 10 Devices
6.4.1.3. On-Chip Termination Recommendations for Cyclone 10 Devices
6.4.1.4. Slew Rates
6.4.2. Channel Signal Integrity Measurement
6.4.2.1. Importance of Accurate Channel Signal Integrity Information
6.4.2.2. Understanding Channel Signal Integrity Measurement
6.4.2.3. How to Enter Calculated Channel Signal Integrity Values
6.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
6.4.3. Layout Approach
6.4.4. Design Layout Guidelines
6.4.4.1. General Layout Guidelines
6.4.4.2. Layout Guidelines
6.4.4.3. Length Matching Rules
6.4.4.4. Spacing Guidelines
6.4.4.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)
6.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
6.4.5. Package Deskew
6.4.5.1. DQ/DQS/DM Deskew
6.4.5.2. Address and Command Deskew
6.4.5.3. Package Deskew Recommendations for Cyclone 10 Devices
6.4.5.4. Deskew Example
6.4.5.5. Package Migration
7. Cyclone 10 GX EMIF IP for LPDDR3
6.1. Parameter Descriptions
7.1.1. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: General
7.1.2. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Memory
7.1.3. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem I/O
7.1.4. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: FPGA I/O
7.1.5. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Mem Timing
7.1.6. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Board
7.1.7. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Controller
7.1.8. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Diagnostics
7.1.9. Intel Cyclone 10 GX EMIF IP LPDDR3 Parameters: Example Designs
6.2. Board Skew Equations
7.2.1. Equations for LPDDR3 Board Skew Parameters
6.3. Pin and Resource Planning
6.3.1. Interface Pins
6.3.1.1. Estimating Pin Requirements
6.3.1.3. Maximum Number of Interfaces
6.3.2. FPGA Resources
6.3.2.1. OCT
6.3.2.2. PLL
6.3.3. Pin Guidelines for Cyclone 10 GX EMIF IP
7.3.1.6.1. General Guidelines
7.3.1.6.2. LPDDR3 Clock Signal
7.3.1.6.3. LPDDR3 Command and Address Signal
7.3.1.6.4. LPDDR3 Data, Data Strobe, and DM Signals
6.3.3.6. Resource Sharing Guidelines (Multiple Interfaces)
7.4. LPDDR3 Board Design Guidelines
6.4.1. Terminations and Slew Rates with Cyclone 10 GX Devices
6.4.1.1. Dynamic On-Chip Termination (OCT) in Cyclone 10 Devices
6.4.1.2. Choosing Terminations on Cyclone 10 Devices
6.4.1.3. On-Chip Termination Recommendations for Cyclone 10 Devices
6.4.2. Channel Signal Integrity Measurement
6.4.2.1. Importance of Accurate Channel Signal Integrity Information
6.4.2.2. Understanding Channel Signal Integrity Measurement
6.4.2.3. How to Enter Calculated Channel Signal Integrity Values
6.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
6.4.3. Layout Approach
6.4.4. Design Layout Guidelines
6.4.4.1. General Layout Guidelines
6.4.4.2. Layout Guidelines
6.4.4.3. Length Matching Rules
6.4.4.4. Spacing Guidelines
6.4.4.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)
6.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
6.4.5. Package Deskew
6.4.5.1. DQ/DQS/DM Deskew
6.4.5.2. Address and Command Deskew
6.4.5.3. Package Deskew Recommendations for Cyclone 10 Devices
6.4.5.4. Deskew Example
6.4.5.5. Package Migration
8. Cyclone 10 GX EMIF IP Timing Closure
8.1. Timing Closure
8.1.1. Timing Analysis
8.1.1.1. PHY or Core
8.1.1.2. I/O Timing
8.1.1.2.1. Read Capture
8.1.1.2.2. Write
8.1.1.2.3. Address and Command
8.1.1.2.4. DQS Gating / Postamble
8.1.1.2.5. Write Leveling
8.2. Timing Report DDR
8.3. Optimizing Timing
8.4. Early I/O Timing Estimation
8.4.1. Performing Early I/O Timing Analysis
9. Optimizing Controller Performance
9.1. Interface Standard
9.2. Bank Management Efficiency
9.3. Data Transfer
9.4. Improving Controller Efficiency
9.4.1. Auto-Precharge Commands
9.4.2. Latency
9.4.2.1. Additive Latency
9.4.3. Calibration
9.4.4. Bank Interleaving
9.4.5. Additive Latency and Bank Interleaving
9.4.6. User-Controlled Refresh
9.4.6.1. Back-to-Back User-Controlled Refresh Usage
9.4.7. Frequency of Operation
9.4.8. Series of Reads or Writes
9.4.9. Data Reordering
9.4.10. Starvation Control
9.4.11. Command Reordering
9.4.12. Bandwidth
9.4.13. Enable Command Priority Control
10. Cyclone 10 GX EMIF IP Debugging
10.1. Interface Configuration Performance Issues
10.1.1. Interface Configuration Bottleneck and Efficiency Issues
10.2. Functional Issue Evaluation
10.2.1. Intel IP Memory Model
10.2.2. Vendor Memory Model
10.2.3. Transcript Window Messages
10.2.4. Modifying the Example Driver to Replicate the Failure
10.3. Timing Issue Characteristics
10.3.1. Evaluating FPGA Timing Issues
10.3.2. Evaluating External Memory Interface Timing Issues
10.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer
10.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer
10.5. Hardware Debugging Guidelines
10.5.1. Create a Simplified Design that Demonstrates the Same Issue
10.5.2. Measure Power Distribution Network
10.5.3. Measure Signal Integrity and Setup and Hold Margin
10.5.4. Vary Voltage
10.5.5. Operate at a Lower Speed
10.5.6. Determine Whether the Issue Exists in Previous Versions of Software
10.5.7. Determine Whether the Issue Exists in the Current Version of Software
10.5.8. Try A Different PCB
10.5.9. Try Other Configurations
10.5.10. Debugging Checklist
10.6. Categorizing Hardware Issues
10.6.1. Signal Integrity Issues
10.6.1.1. Characteristics of Signal Integrity Issues
10.6.1.2. Evaluating SignaI Integrity Issues
10.6.1.2.1. Skew
10.6.1.2.2. Crosstalk
10.6.1.2.3. Power System
10.6.1.2.4. Clock Signals
10.6.1.2.5. Read Data Valid Window and Eye Diagram
10.6.1.2.6. Write Data Valid Window and Eye Diagram
10.6.1.2.7. OCT and ODT Usage
10.6.2. Hardware and Calibration Issues
10.6.2.1. Postamble Timing Issues and Margin
10.6.2.2. Intermittent Issue Evaluation
10.7. Debugging Cyclone 10 GX EMIF IP
10.7.1. Debugging With the External Memory Interface Debug Toolkit
10.7.1.1. User Interface
10.7.1.2. Communication
10.7.1.3. Setup and Use
10.7.1.4. Configuring Your EMIF IP for Use with the Debug Toolkit
10.7.1.4.1. Daisy-Chaining Additional EMIF IP Cores for Debugging
10.7.1.4.2. General Workflow
10.7.1.4.3. Linking the Project to a Device
10.7.1.4.4. Establishing Communication to Connections
10.7.1.4.5. Selecting an Active Interface
10.7.1.5. Reports
10.7.1.6. Driver Margining for Cyclone 10 GX EMIF IP
10.7.1.7. Example Tcl Script for Running the EMIF Debug Toolkit
10.7.2. On-Chip Debug Port for Cyclone 10 GX EMIF IP
10.7.2.1. EMIF On-Chip Debug Port
10.7.2.2. Access Protocol
10.7.3. Efficiency Monitor and Protocol Checker
10.7.3.1. Including the Efficiency Monitor and Protocol Checker in Your Generated IP
10.7.3.2. Running the Efficiency Monitor with the External Memory Debug Toolkit
10.7.3.3. Communicating Directly to the Efficiency Monitor and Protocol Checker
10.8. Using the Traffic Generator with the Generated Design Example
11. External Memory Interfaces Cyclone 10 GX FPGA IP User Guide Archives
12. Document Revision History for Cyclone 10 GX External Memory Interfaces FPGA IP User Guide

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