AN 706: Routing HPS Peripheral Signals to the FPGA External Interface - This document descripts routing of the HPS peripheral signals in the Cyclone devices. - 2018-05-07

1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1.1. Cyclone V and Arria V HPS Peripherals That Support Routing to the FPGA
1.2. Design Example: Cyclone V HPS IP Interface to FPGA
1.2.1. Prerequisites
1.2.1.1. Hardware Requirements
1.2.1.2. Software Requirements
1.2.2. Getting Started
1.2.3. Generating the Initial HDL in Platform Designer (Standard)
1.2.4. Top Level Routing
1.2.5. Timing Constraint Configuration
1.2.6. Adding Pin Assignments in Intel Quartus Prime Standard Edition
1.2.7. Hardware Programming File Compilation and Generation
1.2.8. SD Card Image Updates
1.2.8.1. Preloader Generation
1.2.8.2. U-boot Setup
1.2.8.3. Device Tree Setup
1.2.9. Board Setup and Booting Linux from the SD Card
1.3. Sample Application Example
1.3.1. EMAC Test
1.3.2. I2C Test
1.4. Reference Documents
1.5. AN 706 Revision History

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