AN 810: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report - 2017-12-18

Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Hardware Requirements
Hardware Setup
Hardware Checkout Methodology
Receiver Data Link Layer
Code Group Synchronization (CGS)
Initial Frame and Lane Synchronization (ILA)
Receiver Transport Layer
Descrambling
Deterministic Latency (Subclass 1)
JESD204B IP Core and ADC Configurations
Test Results
Test Result Comments
Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Appendix

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