AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores - Describes the fPLL reconfiguration and dynamic phase shift implementation in Arria V, Cyclone V, and Stratix V device families using the Altera PLL and Altera PLL Reconfig IP cores. - 2019-10-14

Product Type

Device Families > Cyclone Families

Device Families > Arria Families

Device Families > Stratix Families

Device Families > Cyclone Families > Cyclone V

Device Families > Stratix Families > Stratix V

Device Families > Arria Families > Arria V

Resource Type

Documentation > Application Notes

Source Name

DITA