AN 886: Agilex™ 7 Device Design Guidelines - Guidelines, recommendations, and a list of factors to consider for designs that use the Agilex 7 SoC devices. - 2025-12-05
Product Type
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Agilex Families > Agilex 7
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
Documentation > Application Notes
Source Name
DITA
1. Introduction to the Agilex™ 7 Device Design Guidelines
1.1. Design Flow
1.2. Introduction to the Agilex™ 7 Device Design Guidelines Revision History
2. System Specification
2.1. Design Specifications
2.2. Install Quartus Prime Software
2.3. IP Selection
2.3.1. Evaluate Available HPS IP
2.3.2. Select Soft/Hardened IP and I/O Interfaces
2.4. Simulation
2.5. Preparing for Design Entry
2.5.1. Coding Styles and Design Recommendations
2.5.2. Platform Designer
2.6. I/O Summary
2.7. Using Agilex™ 7 HPS in your Device
2.8. System Specification Revision History
3. Device Selection
3.1. Device Variant
3.2. PLLs and Clock Routing
3.3. Logic, Memory, and Multiplier Density
3.4. I/O Pin Count, LVDS SERDES Channels, and Package Offering
3.5. Speed Grade
3.6. Device Migration
3.7. Device Selection Revision History
4. Security Considerations
4.1. Security Considerations Revision History
5. Design Entry
5.1. Design Entry for SoC Devices
5.1.1. Firewall Planning
5.1.2. Boot And Configuration Considerations
5.1.2.1. Selecting HPS Boot Options
5.1.2.2. Configuration Sources
5.1.2.3. Remote System Update (RSU)
5.1.3. HPS Clocking and Reset Design Considerations
5.1.3.1. HPS Clock Planning
5.1.3.2. Early Pin Planning and I/O Assignment Analysis
5.1.3.3. Pin Features and Connections for HPS Clocks, Reset and PoR
5.1.3.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature
5.1.3.5. Internal Clocks
5.1.4. Reset Configuration
5.1.4.1. HPS Peripheral Reset Management
5.1.4.2. System Reset Considerations
5.1.5. HPS Pin Multiplexing Design Considerations
5.1.6. HPS I/O Settings: Constraints and Drive Strengths
5.1.7. Design Guidelines for HPS Interfaces
5.1.7.1. Design Considerations for Selecting PHY Interfaces
5.1.7.1.1. HPS EMAC PHY Interfaces
5.1.7.1.2. RMII and RGMII PHY Interfaces
5.1.7.1.3. PHY Interfaces Connected Through FPGA I/O
5.1.7.1.4. Consider Device Driver Availability
5.1.7.1.5. MDIO
5.1.7.1.6. Signal Integrity
5.1.7.2. USB Interface Design Guidelines
5.1.7.3. SD/MMC and eMMC Card Interface Design Guidelines
5.1.7.4. Design Guidelines for Flash Interfaces
5.1.7.4.1. NAND Flash Interface Design Guidelines
5.1.7.5. UART Interface Design Guidelines
5.1.7.6. I2C Interface Design Guidelines
5.1.8. Interfacing between the FPGA and HPS
5.1.8.1. Overview of HPS Memory-Mapped Interfaces
5.1.8.1.1. HPS-to-FPGA Bridge
5.1.8.1.2. Lightweight HPS-to-FPGA Bridge
5.1.8.1.3. FPGA-to-HPS Bridge
5.1.8.1.4. Interface Bandwidths
5.1.8.2. Recommended System Topologies
5.1.8.2.1. System Level Cache Coherency
5.1.8.2.2. HPS Accesses to FPGA Fabric
5.1.8.2.3. MPU Sharing Data with FPGA
5.1.8.2.4. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
5.1.8.3. Recommended Starting Point for HPS-to-FPGA Interface Designs
5.1.8.4. Information on How to Configure and Use the Bridges
5.1.9. Implementing the Agilex™ 7 HPS Component
5.2. Design Entry for FPGA-only Devices
5.2.1. Clocking and Reset Design Considerations
5.2.2. I/O and Clock Planning
5.2.2.1. Making FPGA Pin Assignments
5.2.2.2. Early Pin Planning and I/O Assignment Analysis for the FPGA Device
5.2.2.3. I/O Features and Pin Connections
5.2.2.3.1. I/O Signaling Type
5.2.2.3.2. Selectable Standards and Flexible I/O Banks
5.2.2.3.3. Dual-Purpose and Special Pin Connections
5.2.2.3.4. Agilex™ 7 I/O Features
5.2.2.4. Clock and PLL Selection
5.2.2.5. PLL Feature Guidelines
5.2.2.5.1. Clock Feedback Mode
5.2.2.5.2. Clock Outputs
5.2.2.6. Clock Control Features
5.2.2.7. I/O Simultaneous Switching Noise
5.3. Design Entry for NoC
5.3.1. NoC Architecture Basics
5.3.2. NoC Design Flow
5.3.3. Configuring NoC IP
5.3.4. Instantiating NoC IP
5.3.5. NoC Assignments
5.3.6. NoC Physical Placement
5.3.7. Compilation
5.3.8. Simulation
5.4. EMIF Considerations
5.4.1. Memory Interfaces
5.4.2. FPGA EMIF Design Considerations
5.5. Nios Software Processor IP
5.5.1. Nios V
5.5.2. Nios II
5.6. Transceiver Planning
5.7. Reconfiguration
5.8. Design Entry Revision History
6. Board and Software Considerations
6.1. Early System and Board Planning
6.1.1. SmartVID
6.1.2. Intel FPGA Power and Thermal Calculator
6.1.3. Thermal Management and Design
6.1.4. Temperature Sensing for Thermal Management
6.1.5. Voltage Sensor
6.1.6. Device Power-Up
6.1.7. Power Pin Connections and Power Supplies
6.1.7.1. Decoupling Capacitors
6.1.7.2. PLL Board Design Guidelines
6.1.7.3. Transceiver Board Design Guidelines
6.1.8. Planning for Device Configuration
6.1.8.1. Device Power Cycling and Reconfiguration
6.1.8.2. Configuration Scheme Selection
6.1.8.2.1. Serial Configuration Devices
6.1.8.2.2. Altera FPGA Download Cable
6.1.8.3. Configuration Features
6.1.8.4. Quartus Prime Configuration Settings
6.1.8.4.1. Optional Configuration Pins
6.1.8.4.2. Dual Purpose Configuration Pins
6.1.8.5. Configuration Pin Connections
6.1.8.5.1. Configuration Pin Voltage Level
6.1.8.5.2. Clock Trace Signal Integrity
6.1.8.5.3. JTAG Pins
6.1.8.5.3.1. JTAG Pin Connections
6.1.8.5.3.2. Download Cable Operating Voltage
6.1.8.5.3.3. JTAG Signal Buffering
6.1.8.5.4. MSEL Configuration Mode Pins
6.1.8.5.5. Other Configuration Pins
6.2. Board Design Guidelines for Agilex™ 7 SoC FPGAs
6.2.1. Boundary Scan for HPS
6.2.2. Embedded Software Debugging and Trace
6.3. Pin Connection Considerations for Board Design
6.3.1. Board-Related Quartus Prime Settings
6.3.1.1. Unused Pins
6.3.2. Signal Integrity Considerations
6.3.2.1. High-Speed Board Design
6.3.2.2. Voltage Reference Pins
6.3.2.3. Simultaneous Switching Noise
6.3.2.4. I/O Termination
6.3.3. Board-Level Simulation and Advanced I/O Timing Analysis
6.4. Board Considerations Revision History
7. Design Implementation, Analysis, Optimization, and Verification
7.1. Selecting a Synthesis Tool
7.2. Device Resource Utilization Reports
7.3. Quartus Prime Messages
7.4. Timing Constraints and Analysis
7.4.1. Recommended Timing Optimization and Analysis Assignments
7.5. Area and Timing Optimization
7.6. Preserving Performance and Reducing Compilation Time
7.7. Designing with Hyperflex
7.8. Simulation
7.9. Power Analysis
7.10. Power Optimization
7.10.1. Device and Design Power Optimization Techniques
7.10.1.1. Device Speed Grade
7.10.1.2. Clock Power Management
7.10.1.3. Memory Power Reduction
7.10.1.4. I/O Power Guidelines
7.10.2. Quartus Prime Power Optimization Techniques
7.11. Design Implementation, Analysis, Optimization, and Verification Revision History
8. Debugging
8.1. On-Chip Debug Overview
8.1.1. Planning Guidelines for Debugging Tools
8.2. On-Chip Debugging Tools
8.3. Debugging Revision History
9. Embedded Software Design Guidelines for Agilex™ 7 SoC FPGAs
9.1. Overview
9.2. Golden Hardware Reference Design (GHRD)
9.3. Define Software Requirements
9.4. Define Software Architecture
9.5. Selecting Software Tools
9.5.1. Selecting Software Build Tools
9.5.2. Selecting Software Debug Tools
9.5.3. Selecting Software Trace Tools
9.6. Choosing the Bootloader Software
9.7. Selecting an Operating System for Your Application
9.7.1. Using Linux or RTOS
9.7.2. Using the Bootloader as a Bare-Metal Framework
9.7.3. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
9.8. Assembling Your Software Development Platform for Linux
9.8.1. Golden System Reference Design (GSRD) for Linux
9.8.2. Source Code Management Considerations
9.9. Assembling your Software Development Platform for Partner OS or RTOS
9.10. Driver Considerations
9.11. Boot And Configuration Considerations
9.11.1. Configuration Sources
9.11.2. Configuration Flash
9.11.3. Configuration Clock
9.11.4. Selecting HPS Boot Options
9.11.5. HPS Boot Sources
9.11.6. Remote System Update (RSU)
9.12. System Reset Considerations
9.13. Flash Considerations
9.13.1. Flash Programming Method
9.13.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
9.14. Develop Application
9.15. Test and Validate
9.16. Embedded Software Design Guidelines Revision History