AN 779: JESD204B IP Core and ADI AD9691 Hardware Checkout Report - 2017-12-18

1. Altera FPGA JESD204B IP Core and AD9691 Hardware Checkout Report
1.1. Hardware Requirements
1.2. Hardware Setup
1.3. Hardware Checkout Methodology
1.3.1. Receiver Data Link Layer
1.3.1.1. Code Group Synchronization (CGS)
1.3.1.2. Initial Frame and Lane Synchronization
1.3.2. Receiver Transport Layer
1.3.3. Descrambling
1.3.4. Deterministic Latency (Subclass 1)
1.4. JESD204B IP Core and ADC Configurations
1.5. Test Results
1.6. Test Result Comments
1.7. Document Revision History for AN 779: Altera FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

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