You can simulate your Interlaken IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the new <instance name>/sim/<simulator> subdirectory of your project directory.
The F-Tile Interlaken IP supports the following simulators:
- Synopsys® VCS® and VCS® MX
- Siemens® EDA QuestaSIM®
- Cadence* Xcelium™
- Questa*-Altera FPGA Edition
The F-Tile Interlaken IP generates a Verilog HDL and VHDL simulation model and testbench. The IP parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP, but the IP design example does not support a VHDL simulation model or testbench.
For more information about functional simulation models for Altera FPGA IPs, refer to the Simulating FPGA Designs chapter in Quartus Prime Pro Edition User Guide: Third-party Simulation.