6. F-Tile Interlaken IP Registers - 2025-12-15

The IP control registers are 32 bits wide and are accessible to you using the management interface, an Avalon^® memory-mapped interface which conforms to the Avalon Interface Specifications.

• F-Tile Interlaken IP Register Map

The FGT and FHT PMA registers are 32 bits wide and are accessible to you using the Transceiver Reconfiguration Interface, an Avalon^® memory-mapped interface which conforms to the Avalon Interface Specifications.

• F-Tile PMA/FEC Direct PHY IP Register Map

The FEC registers are 32 bits wide and are accessible to you using the Interlaken Reconfiguration Interface, an Avalon^® memory-mapped interface which conforms to the Avalon Interface Specifications.

• F-Tile Ethernet Hard IP Register Map