AN 951: Stratix 10 I/O Limited FPGA Design Guidelines - Design guidelines for Stratix 10 I/O Limited (IOL) FPGAs. - 2021-08-24

Version: 21.1

1. Introduction
2. Overview
2.1. Available Device Options and Ordering Part Numbers
3. Quartus Prime Software Guidelines
3.1. Design Migration
3.2. Quartus Prime Software Patch Compatibility
3.3. Related Quartus Prime Software Error Messages
4. Device Guidelines
4.1. Device Configuration Guidelines
4.2. GPIO and LVDS Guidelines
4.2.1. I/O Resource Comparison Between Standard OPN and IOL OPN Devices
4.2.2. Design Migration
4.2.3. Error Message for > 700 Pins Utilization
4.3. Transceiver Guidelines
4.3.1. Transceiver Bandwidth Calculation
4.4. Error Message for Design Exceeding Maximum Transceiver Bandwidth
5. Document Revision History for AN 951: Stratix 10 I/O Limited FPGA Design Guidelines

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