Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide - Describes a simulatable testbench and a hardware design example that supports compilation and hardware testing for prototyping ASIC devices in the Low Latency 40G Ethernet IP. - 2020-10-05

Version

20.3

Product Type

Device Families > Stratix Families

Device Families > Stratix Families > Stratix 10

Resource Type

Documentation > User Guides

Source Name

DITA