4.4. SDI Transceiver Dynamic Reconfiguration Signals

These signals handle the transceiver dynamic reconfiguration operation.

Table 18. SDI Transceiver Dynamic Reconfiguration Signals
Signal	Direction	Description
`SDI_RECONFIG_DONE`	Input	Indicates back to the IP core that reconfiguration has finished. This signal is not required for PLL reconfiguration.
`SDI_RECONFIG_TOGXB` Note: Connect this signal directly to a reconfiguration megafunction.	Input	Data input for the embedded transceiver instance. Data width: For Arria V, Cyclone V, and Stratix V devices = `SDI_RECONFIG_TOGXB[(140N-1)]:0]` or `SDI_RECONFIG_TOGXB[(70N-1)]:0]`—if you select the receiver in the interface settings. For other supported devices = `SDI_RECONFIG_TOGXB[3:0]` Note: SDI transmitters do not require the use of transceiver dynamic reconfiguration. However, to enable the cores to merge into a transceiver quad that has transceiver dynamic reconfiguration enabled, you must connect these ports correctly.
`SDI_RECONFIG_CLK`	Input	Clock input for the embedded transceiver instance. Note: This signal is not applicable for Arria V, Cyclone V, and Stratix V devices. Note: SDI transmitters do not require the use of transceiver dynamic reconfiguration. However, to enable the cores to merge into a transceiver quad that has transceiver dynamic reconfiguration enabled, you must connect these ports correctly.
`SDI_GXB_POWERDOWN`	Input	Powers down and resets circuits in all transceiver instance. Note: This signal is not applicable for Arria V, Cyclone V, and Stratix V devices.
`SDI_START_RECONFIG`	Output	Request from the IP core to start reconfiguration.
`SDI_RECONFIG_FROMGXB` Note: Connect this signal directly to a reconfiguration megafunction.	Output	Data output from the embedded transceiver instance. Data width: For Arria V, Cyclone V, and Stratix V devices = `SDI_RECONFIG_FROMGXB[(92N-1):0]` or `SDI_RECONFIG_FROMGXB[(46N-1):0]`—if you select the receiver in the interface settings. For other supported devices = `SDI_RECONFIG_FROMGXB[(17N-1):0]`; `SDI_RECONFIG_FROMGXB[16:5]` are negligible for Cyclone IV GX devices. Note: SDI transmitters do not require the use of transceiver dynamic reconfiguration. However, to enable the cores to merge into a transceiver quad that has transceiver dynamic reconfiguration enabled, you must connect these ports correctly.
`RX_STD[1:0]`	Output	Receive video standard. 00 = SD-SDI, 01 = HD-SDI, 10 = 3G-SDI. The SDI IP core can recover both SMPTE 425M-A and 425M-B formatted streams. The receiver indicates which format it detects by setting the level of the `rx_std` bus: `rx_std[1:0]` = 2’b11 = 425M-A `rx_std[1:0]` = 2’b10 = 425M-B
`PLL_ARESET`	Input	Drives the `areset` signal on the transceiver PLL to be reconfigured. This signal indicates that the transceiver PLL must be reset. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_CONFIGUPDATE`	Input	Drives the `configupdate` signal on the transceiver PLL to be reconfigured. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_SCANCLK`	Input	Drives the `scanclk` signal on the transceiver PLL to be reconfigured. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_SCANCLKENA`	Input	Acts as a clock enable for the `scanclk` signal on the transceiver PLL to be reconfigured. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_SCANDATA`	Input	Drives the `scandata` signal on the transceiver PLL to be reconfigured. This signal holds the scan data input to the transceiver PLL for the dynamically reconfigurable bits. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_SCANDONE`	Output	Determines when the transceiver PLL is reconfigured. Note: The transceivers are available for Cyclone IV GX devices only.
`PLL_SCANDATAOUT`	Output	This signal holds the transceiver PLL scan data output from the dynamically reconfigurable bits. Note: The transceivers are available for Cyclone IV GX devices only.

Note: In the Intel^® Quartus^® Prime software version 8.1 and later, the Stratix IV transceivers require receiver buffer calibration through an ALTGX_RECONFIG(transceiver dynamic reconfiguration) controller. The additional RECONFIG port bits are used for receiver buffer calibration. The additional RECONFIG port bits are used for receiver buffer calibration. You must connect these ports to the ALTGX_RECONFIG controller externally.

If you are using Cyclone IV devices, you would require the following additional signals.

Connect these signals directly to the ALTPLL_RECONFIG IP core and expose the signals to the top level when you select the Use PLL reconfiguration for transceiver dynamic reconfiguration option in the SDI parameter editor.

Table 19. SDI Transceiver Dynamic Reconfiguration Signals—for Cyclone IV GX DevicesYou require `rx_std` and `sdi_start_reconfig` signals for PLL reconfiguration.
Signal	Direction	Description
`PLL_ARESET`	Input	Drives the `areset` signal on the transceiver PLL to be reconfigured. This signal indicates that the transceiver PLL must be reset.
`PLL_CONFIGUPDATE`	Input	Drives the `configupdate` signal on the transceiver PLL to be reconfigured.
`PLL_SCANCLK`	Input	Drives the `scanclk` signal on the transceiver PLL to be reconfigured.
`PLL_SCANCLKENA`	Input	Acts as a clock enable for the `scanclk` signal on the transceiver PLL to be reconfigured.
`PLL_SCANDATA`	Input	Drives the `scandata` signal on the transceiver PLL to be reconfigured. This signal holds the scan data input to the transceiver PLL for the dynamically reconfigurable bits.
`PLL_SCANDONE`	Output	Determines when the transceiver PLL is reconfigured.
`PLL_SCANDATAOUT`	Output	This signal holds the transceiver PLL scan data output from the dynamically reconfigurable bits.

4.4. SDI Transceiver Dynamic Reconfiguration Signals - 2025-12-16

SDI IP Core User Guide