Cyclone V Device Handbook Volume 2: Transceivers - Describes the Cyclone V transceiver architecture, clocking, channels, channel bonding, and transmitter and receiver channel datapaths. - 2018-10-24

1. Transceiver Architecture in Cyclone V Devices
1.1. Architecture Overview
1.1.1. Transceiver Banks
1.1.1.1. Usage Restrictions on Specific Channels
1.1.2. 6.144 Gbps CPRI Support Capability in GT Devices
1.1.3. Transceiver Channel Architecture
1.2. PMA Architecture
1.2.1. Transmitter PMA Datapath
1.2.1.1. Serializer
1.2.1.1.1. Transmitter Polarity Inversion
1.2.1.1.2. Bit Reversal
1.2.1.2. Transmitter Buffer
1.2.1.2.1. Transmitter Buffer Features and Capabilities
1.2.1.2.2. Programmable Transmitter Analog Settings
1.2.1.2.3. Programmable Transmitter VCM
1.2.1.2.4. Programmable Transmitter Differential OCT
1.2.1.2.5. Transmitter Protocol Specific
1.2.2. Receiver PMA Datapath
1.2.2.1. Receiver Buffer
1.2.2.1.1. Programmable CTLE and DC Gain
1.2.2.1.2. Programmable Receiver VCM
1.2.2.1.3. Programmable Receiver Differential On-Chip Termination
1.2.2.1.4. Signal Threshold Detection Circuitry
1.2.2.2. Deserializer
1.2.2.2.1. Clock-slip
1.2.3. Transmitter PLL
1.2.3.1. Channel PLL Architecture
1.2.3.2. Channel PLL as CDR PLL
1.2.3.2.1. Lock-to-Reference Mode
1.2.3.2.2. Lock-to-Data Mode
1.2.3.2.3. CDR PLL in Automatic Lock Mode
1.2.3.2.4. CDR PLL in Manual Lock Mode
1.2.3.3. Channel PLL as a CMU PLL
1.2.3.4. fPLL as a Transmitter PLL
1.2.4. Clock Divider
1.2.5. Calibration Block
1.3. PCS Architecture
1.3.1. Transmitter PCS Datapath
1.3.1.1. Transmitter Phase Compensation FIFO
1.3.1.1.1. Registered Mode
1.3.1.1.2. Phase Compensation Mode
1.3.1.2. Byte Serializer
1.3.1.2.1. Byte Serializer in Single-Width Mode
1.3.1.2.2. Byte Serializer in Double-Width Mode
1.3.1.3. 8B/10B Encoder
1.3.1.3.1. 8B/10B Encoder in Single-Width Mode
1.3.1.3.2. 8B/10B Encoder in Double-Width Mode
1.3.1.3.3. Running Disparity Control
1.3.1.3.4. Control Code Encoding
1.3.1.3.5. Reset Condition
1.3.1.3.6. Encoder Output During Reset Sequence
1.3.1.4. Transmitter Bit-Slip
1.3.2. Receiver PCS Datapath
1.3.2.1. Word Aligner
1.3.2.1.1. Word Aligner Options and Behaviors
1.3.2.1.2. Word Aligner in Manual Alignment Mode
1.3.2.1.3. Word Aligner in Bit-Slip Mode
1.3.2.1.4. Word Aligner in Automatic Synchronization State Machine Mode
1.3.2.1.5. Word Aligner in Automatic Synchronization State Machine Mode with a 10-Bit PMA-PCS Interface Configuration
1.3.2.1.6. Word Aligner Operations in Deterministic Latency State Machine Mode
1.3.2.1.7. Programmable Run-Length Violation Detection
1.3.2.1.8. Receiver Polarity Inversion
1.3.2.1.9. Bit Reversal
1.3.2.1.10. Receiver Byte Reversal
1.3.2.2. Rate Match FIFO
1.3.2.3. 8B/10B Decoder
1.3.2.3.1. 8B/10B Decoder in Single-Width Mode
1.3.2.3.2. 8B/10B Decoder in Double-Width Mode
1.3.2.3.3. Control Code Group Detection
1.3.2.4. Byte Deserializer
1.3.2.4.1. Byte Deserializer in Single-Width Mode
1.3.2.4.2. Byte Deserializer in Double-Width Mode
1.3.2.5. Byte Ordering
1.3.2.5.1. Byte Ordering in Single-Width Mode
1.3.2.5.2. Byte Ordering in Double-Width Mode
1.3.2.5.3. Word Aligner-Based Ordering Mode
1.3.2.5.4. Manual Ordering Mode
1.3.2.6. Receiver Phase Compensation FIFO
1.3.1.1.1. Registered Mode
1.4. Channel Bonding
1.5. PLL Sharing
1.6. Document Revision History
2. Transceiver Clocking in Cyclone V Devices
2.1. Input Reference Clocking
2.1.1. Dedicated Reference Clock Pins
2.1.1.1. Dedicated refclk Using the Reference Clock Network
2.1.1.2. Dual-Purpose RX/refclk Pins
2.1.2. Fractional PLL (fPLL)
2.2. Internal Clocking
2.2.1. Transmitter Clock Network
2.2.2. Transmitter Clocking
2.2.2.1. Non-Bonded Channel Configurations
2.2.2.2. Bonded Channel Configurations
2.2.3. Receiver Clocking
2.2.3.1. Receiver Non-Bonded Channel Configurations
2.2.3.2. Receiver Bonded Channel Configurations
2.3. FPGA Fabric–Transceiver Interface Clocking
2.3.1. Transceiver Datapath Interface Clocking
2.3.2. Transmitter Datapath Interface Clocking
2.3.2.1. Quartus II-Software Selected Transmitter Datapath Interface Clock
2.3.2.2. Selecting a Transmitter Datapath Interface Clock
2.3.3. Receiver Datapath Interface Clock
2.3.3.1. Quartus II Software-Selected Receiver Datapath Interface Clock
2.3.3.2. Selecting a Receiver Datapath Interface Clock
2.4. Document Revision History
3. Transceiver Reset Control in Cyclone V Devices
3.1. PHY IP Embedded Reset Controller
3.1.1. Embedded Reset Controller Signals
3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up
3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller
3.2.1. User-Coded Reset Controller Signals
3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up
3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation
3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration
3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode
3.4.1. Control Settings for CDR Manual Lock Mode
3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
3.5. Resetting the Transceiver During Dynamic Reconfiguration
3.6. Transceiver Blocks Affected by the Reset and Powerdown Signals
3.7. Transceiver Power-Down
3.8. Document Revision History
4. Transceiver Protocol Configurations in Cyclone V Devices
4.1. PCI Express
4.1.1. PCIe Transceiver Datapath
4.1.2. PCIe Supported Features
4.1.2.1. PIPE Interface
4.1.2.2. Transmitter Electrical Idle Generation
4.1.2.3. Power State Management
4.1.2.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
4.1.2.5. Receiver Status
4.1.2.6. Receiver Detection
4.1.2.7. Clock Rate Compensation Up to ±300 ppm
4.1.2.8. PCIe Reverse Parallel Loopback
4.1.3. PCIe Supported Configurations and Placement Guidelines
4.2. Gigabit Ethernet
4.2.1. Gigabit Ethernet Transceiver Datapath
4.3. XAUI
4.3.1. Transceiver Datapath in a XAUI Configuration
4.3.2. XAUI Supported Features
4.3.3. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
4.4. Serial Digital Interface
4.4.1. Configurations Supported in SDI Mode
4.4.2. Serial Digital Interface Transceiver Datapath
4.5. Serial Data Converter (SDC) JESD204
4.6. SATA and SAS Protocols
4.7. Deterministic Latency Protocols—CPRI and OBSAI
4.7.1. Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode
4.7.2. Channel PLL Feedback for Deterministic Relationship
4.7.3. CPRI and OBSAI
4.7.4. 6.144-Gbps Support Capability in Cyclone V GT Devices
4.7.5. CPRI Enhancements
4.8. Document Revision History
5. Transceiver Custom Configurations in Cyclone V Devices
5.1. Standard PCS Configuration
5.1.1. Custom Configuration Channel Options
5.1.2. Rate Match FIFO in Custom Configuration
5.1.2.1. Rate Match FIFO Behaviors in Custom Single-Width Mode
5.1.2.2. Rate Match FIFO Behaviors in Custom Double-Width Mode
5.2. Standard PCS in Low Latency Configuration
5.2.1. Low Latency Custom Configuration Channel Options
5.3. Document Revision History
6. Transceiver Loopback Support
6.1. Serial Loopback
6.2. Forward Parallel Loopback
6.3. PIPE Reverse Parallel Loopback
6.4. Reverse Serial Loopback
6.5. Reverse Serial Pre-CDR Loopback
6.6. Document Revision History
7. Dynamic Reconfiguration in Cyclone V Devices
7.1. Dynamic Reconfiguration Features
7.2. Offset Cancellation
7.3. Transmitter Duty Cycle Distortion Calibration
7.4. PMA Analog Controls Reconfiguration
7.5. Dynamic Reconfiguration of Loopback Modes
7.6. Transceiver PLL Reconfiguration
7.7. Transceiver Channel Reconfiguration
7.8. Transceiver Interface Reconfiguration
7.9. Reduced .mif Reconfiguration
7.10. Unsupported Reconfiguration Modes
7.11. Document Revision History

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