The figure below shows the SR-IOV design example simulation design hierarchy. The tests for the SR-IOV design example are defined with the apps_type_hwtcl parameter set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar and downstream_loop.
Figure 30. SR-IOV Design Example Simulation Design Hierarchy
Device Under Test
Test Driver Module
The SR-IOV testbench supports up to two Physical Functions and 16 Virtual Functions per PF.
The testbench starts with link training and then accesses the configuration
space of the R-Tile PCIe IP for enumeration. After that, it performs the following steps:
- Sends a memory write request to a PF followed by a memory read request to read back the same data for comparison. The test passes if the read data matches the write data.
- Sends a memory write request to a VF followed by a memory read request to read back the data for comparison. The test passes if the read data matched the write data. This test is repeated for each VF.