AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP - Provides guidelines to scale up the single link in the JESD204C RX IP design example generated from the Quartus Prime software to handle a dual link system. - 2024-11-30
- Product Type
- Device Families > Agilex Families
- Device Families > Agilex Families > Agilex 7 > F-Series
- Device Families > Agilex Families > Agilex 7
- Resource Type
- Documentation > Application Notes
- Source Name
- DITA