L-Tile and H-Tile Avalon Memory-mapped+ Intel FPGA IP for PCI Express User Guide - This IP contains a configurable, hardened protocol stack that is compliant with the PCI Express Base Specification and supports Avalon memory mapped and Avalon memory mapped DMA interfaces to the application in the FPGA core running at up to Gen3 x16. - 2024-09-13

Version

23.4

Product Type

Device Families > Stratix Families > Stratix 10

Device Families > Stratix Families

Resource Type

Documentation > User Guides

Source Name

DITA