Stratix 10 General Purpose I/O User Guide - Describes the Stratix 10 device family's general purpose I/Os and the GPIO Intel FPGA IP , their architecture, vertical migrations, supported I/O standards and voltages, programmable features, termination, design guidelines and examples, parameter options and signals, and steps to migrate from the ALTDDIO_IN , ALTDDIO_OUT , ALTDDIO_BIDIR , and ALTIOBUF IPs. - 2024-10-07
Version
24.3
1. Stratix 10 I/O Overview
1.1. Stratix 10 I/O and Differential I/O Buffers
1.2. Stratix 10 I/O Migration Support
2. Stratix 10 I/O Architecture and Features
2.1. I/O Standards and Voltage Levels in Stratix 10 Devices
2.1.1. Stratix 10 I/O Standards Support
2.1.2. Stratix 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Stratix 10 Devices
2.2.1. I/O Bank Architecture in Stratix 10 Devices
2.2.2. I/O Buffer and Registers in Stratix 10 Devices
2.3. Programmable IOE Features in Stratix 10 Devices
2.3.1. Programmable Output Slew Rate Control
2.3.2. Programmable IOE Delay
2.3.3. Programmable Open-Drain Output
2.3.4. Programmable Bus Hold
2.3.5. Programmable Pull-Up Resistor
2.3.6. Programmable Pre-Emphasis
2.3.7. Programmable Differential Output Voltage
2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Stratix 10 Devices
2.4.1. RS OCT without Calibration in Stratix 10 Devices
2.4.2. RS OCT with Calibration in Stratix 10 Devices
2.4.3. RT OCT with Calibration in Stratix 10 Devices
2.4.4. Dynamic OCT
2.4.5. Differential Input RD OCT
2.4.6. OCT Calibration Block in Stratix 10 Devices
2.5. External I/O Termination for Stratix 10 Devices
2.5.1. Single-Ended I/O Termination
2.5.2. Differential I/O Termination for Stratix 10 Devices
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination
2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination
2.5.2.3. LVPECL Termination
3. Stratix 10 I/O Design Considerations
3.1. Guideline: VREF Sources and VREF Pins
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
3.5. Guideline: Stratix 10 I/O Buffer During Power Up, Configuration, and Power Down
3.6. Guideline: Maximum DC Current Restrictions
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Stratix 10 TX 400
3.9. Guideline: I/O Standards Limitation for Stratix 10 GX 400 and SX 400
4. Stratix 10 I/O Implementation Guides
4.1. GPIO Intel FPGA IP
4.1.1. Release Information for GPIO Intel FPGA IP
4.1.2. GPIO Intel FPGA IP Data Paths
4.1.2.1. Input Path
4.1.2.2. Output and Output Enable Paths
4.1.3. Register Packing
4.2. Verifying Resource Utilization and Design Performance
4.3. GPIO Intel FPGA IP Timing
4.3.1. Timing Components
4.3.2. Delay Elements
4.3.3. Timing Analysis
4.3.3.1. Single Data Rate Input Register
4.3.3.2. Full-Rate or Half-Rate DDIO Input Register
4.3.3.3. Single Data Rate Output Register
4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.3.4. Timing Closure Guidelines
4.4. GPIO Intel FPGA IP Design Examples
4.4.1. GPIO Intel FPGA IP Synthesizable Quartus Prime Design Example
4.4.2. GPIO Intel FPGA IP Simulation Design Example
4.5. Verifying Pin Migration Compatibility
4.6. IP Migration to the GPIO IP Core
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores
4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel FPGA IP Reference
5.1. GPIO Intel FPGA IP Parameter Settings
5.2. GPIO Intel FPGA IP Interface Signals
5.2.1. Shared Signals
5.2.2. Data Bit-Order for Data Interface
5.2.3. Data Interface Signals and Corresponding Clocks
6. Document Revision History for the Stratix 10 General Purpose I/O User Guide