3.2. Generating the Example Design using Quartus Prime - 2026-01-07

Multi Channel DMA IP for PCI Express* Design Example User Guide

Version: 25.3.1

1. Introduction
1.1. Terms and Acronyms
1.2. MCDMA IP Modes
2. Design Example Detailed Description
2.1. Design Example Overview
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint
2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint
2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint
2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint
2.1.5. Design Example BAR Mappings
2.1.6. Design Example Driver Support
2.2. PIO using MCDMA Bypass Mode
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode
2.2.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.2.2. Avalon-MM PIO using MCDMA Bypass Mode
2.2.2.1. Simulation Results
2.2.2.2. Hardware Test Results
2.3. Avalon-ST Packet Generate/Check
2.3.1. Single-Port Avalon-ST Packet Generate/Check
2.3.1.1. Simulation Waveforms
2.3.1.2. Simulation Log
2.3.1.3. Hardware Test Result
2.4. Avalon-ST Device-side Packet Loopback
2.4.1. Simulation Results
2.4.2. Hardware Test Results
2.5. Avalon-MM DMA
2.5.1. Simulation Results
2.5.2. Hardware Test Results
2.6. BAM_BAS Traffic Generator and Checker
2.6.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.7. External Descriptor Controller
2.7.1. Registers
2.7.1.1. GCSR Registers (Base address 64’h00000)
2.7.1.2. QCSR Registers(Base address 64’h10000)
2.7.2. Hardware Test Results
3. Design Example Quick Start Guide
3.1. Design Example Directory Structure
3.2. Generating the Example Design using Quartus Prime
3.2.1. Procedure
3.3. Simulating the Design Example
3.3.1. Testbench Overview
3.3.2. Supported Simulators
3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example
3.3.4. Run the Simulation Script
3.3.5. Steps to Run the Simulation
3.3.5.1. Steps to Run the Simulation : QuestaSIM / Questa – Altera FPGA Edition
3.3.5.2. Steps to Run the Simulation : VCS / VCS MX
3.3.5.3. Steps to Run the Simulation : Xcelium
3.3.6. View the Results
3.4. Compiling the Example Design in Quartus Prime
3.5. Running the Design Example Application on a Hardware Setup
3.5.1. Hardware Requirements
3.5.2. Software Requirements
3.5.3. Set Up the Hardware and Program the FPGA
3.5.4. Configuration Changes from BIOS
3.5.5. Installing the Required Kernel Version for Ubuntu v24.04
3.5.6. Set the Boot Parameters
3.5.7. MCDMA Custom Driver
3.5.7.1. Prerequisites
3.5.7.1.1. Install the Linux Kernel Driver
3.5.7.1.2. Enable Virtual Function
3.5.7.1.3. Build and Install the User Space Library
3.5.7.1.4. Build the Reference Application
3.5.7.2. PIO Test
3.5.7.2.1. Custom PIO Read Write Test
3.5.7.3. DMA Test
3.5.7.3.1. Avalon-MM DMA (AVMM DMA)
3.5.7.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback)
3.5.7.3.2.1. DMA Test Beyond 256 Channels
3.5.7.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check)
3.5.7.3.3.1. DMA Test Beyond 256 Channels
3.5.7.3.4. External Descriptor Controller
3.5.7.4. BAM Test
3.5.7.5. BAS Test
3.5.8. MCDMA DPDK Poll Mode Driver
3.5.8.1. Prerequisites
3.5.8.1.1. Install the PMD Driver
3.5.8.1.2. Bind the Device
3.5.8.1.3. Enable Virtual Function
3.5.8.2. PIO Test
3.5.8.3. DMA Test
3.5.8.3.1. Avalon-MM DMA (AVMM DMA)
3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check)
3.5.8.3.2.1. DMA Test Beyond 256 Channels
3.5.8.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback)
3.5.8.3.3.1. DMA Test Beyond 256 Channels
3.5.8.4. BAM Test
3.5.8.5. BAS Test
3.5.9. MCDMA Kernel Mode Network Device Driver
3.5.9.1. Prerequisites
3.5.9.1.1. Build and Install Netdev Driver
3.5.9.1.2. Enable Virtual Function
3.5.9.2. PIO Test
3.5.9.3. Ping Test
4. Multi Channel DMA FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA FPGA IP for PCI Express Design Example User Guide

Figure 26. Design Example Generation

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