3. Design Example Quick Start Guide - 2026-09-17

Multi Channel DMA IP for PCI Express* Design Example User Guide
Version
25.3.1
Product Type
Device Families > Agilex Families > Agilex 7 > M-Series
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Stratix Families > Stratix 10
Device Families > Agilex Families > Agilex 7
Device Families > Stratix Families
Device Families > Agilex Families > Agilex 7 > I-Series
Resource Type
Documentation > User Guides
ft:sourceName
DITA

Using Quartus® Prime software, you can generate a design example for the Multi Channel DMA for PCI Express® ( PCIe® ) IP core.

The generated design example reflects the parameters that you specify. The design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to your FPGA Development Board. To download to custom hardware, update the Quartus® Prime Settings File (.qsf) with the correct pin assignments.

Figure 25. Design Example Development Steps