3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) - 2026-01-07

Multi Channel DMA IP for PCI Express* Design Example User Guide

Version
25.3.1

The DPDK driver can be used with the AVST/AXIST Packet Generate/Check design example to test the packet generator and checker design. The following diagram shows the testing strategy.

  1. Update the static channel mapping in

    p0_software/dpdk/dpdk/examples/mcdma-test/perfq/perfq_app.h by modifying the following parameters:

    •	/* PF count starts from 1 */
    #define IFC_QDMA_CUR_PF <pf number>
    •	/* VF count starts from 1. Zero implies PF was used instead of VF */
    #define IFC_QDMA_CUR_VF <vf number>
    •	/* Number of PFs */
    #define IFC_QDMA_PFS <number of PFs>
    /* Channels available per PF */
    #define IFC_QDMA_PER_PF_CHNLS <number of channels per PF>
    •	/* Channels available per VF */
    #define IFC_QDMA_PER_VF_CHNLS <number of channels per VF>
    •	/* Number of VFs per PF */
    #define IFC_QDMA_PER_PF_VFS <number of VFs per PF>
    
  2. Ensure that the steps outlined in the Prerequisites section are completed before verifying the Packet Generate/Check design example. Alternatively, you may use the driver installation script located at p0_software/DriverLoadUnload.sh.
    1. To allow the script execution, run the command below:

      $ chmod +x DriverLoadUnload.sh

    2. Run the script, then select the desired driver type to proceed with the installation.

      $ ./DriverLoadUnload.sh

    Note: Driver installation requires entering the sudo password.
  3. Run the following commands to check if the setup works correctly after the driver installation above:

    $ cd p0_software/dpdk/dpdk/patches/v21.11.2/dpdk-stable/build/examples/mcdma-test/perfq

    $sudo ./build/mcdma-test -m 8192 --file-prefix=pf0 -- -b 0000:01:00.0 \ -p 32768 -d 2 -c 1 -a 2 -l 5 -z -n

    Configuration:
    • 1 DMA channel (-c 1)
    • Packet generator bidirectional (-z)
    • Payload length of 32,768 bytes in each descriptor (-p 32768)
    • Transfer the data every 5 seconds (-l 5)
    • Dump the progress log every 2 seconds (-d 2)
    • Configure the number of channels in ED (-n)
    • Number of threads to be used for DMA purpose (-a 2)
Figure 43. DPDK Avalon-ST Packet Generate/Check Design Example Gen4 x16: P-Tile Hardware Test Results