V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide - Hard IP for PCI Express Endpoint and Root Port, Gen1, Gen2, Gen3 - 2018-07-31

Version: 16.1

1. Datasheet
1.1. V-Series Avalon-MM DMA Interface for PCIe Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces for V-Series Devices
1.4. Release Information
1.5. V-Series Device Family Support
1.6. Design Examples
1.7. Debug Features
1.8. IP Core Verification
1.8.1. Compatibility Testing Environment
1.9. Resource Utilization
1.10. V-Series Recommended Speed Grades
1.11. Creating a Design for PCI Express
2. Getting Started with the Avalon-MM DMA
2.1. Understanding the Avalon-MM DMA Ports
2.2. Generating the Testbench
2.2.1. Understanding the Simulation Generated Files
2.2.2. Understanding Simulation Log File Generation
2.3. Simulating the Example Design in ModelSim
2.4. Running a Gate-Level Simulation
2.5. Generating Synthesis Files
2.6. Compiling the Design
2.7. Creating a Quartus Prime Project
3. Parameter Settings
3.1. System Settings
3.2. Base Address Register (BAR) Settings
3.3. Device Identification Registers
3.4. PCI Express and PCI Capabilities Parameters
3.4.1. Device Capabilities
3.4.2. Error Reporting
3.4.3. Link Capabilities
3.4.4. MSI and MSI-X Capabilities
3.4.5. Power Management
3.5. PCIe Address Space Settings
4. IP Core Interfaces
4.1. V-Series DMA Avalon-MM DMA Interface to the Application Layer
4.1.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated
4.1.2. Read Data Mover
4.1.3. Write DMA Avalon-MM Master Port
4.1.4. RX Master Module
4.1.5. Non-Bursing Slave Module
4.1.6. 32-Bit Control Register Access (CRA) Slave Signals
4.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately
4.1.7.1. Avalon-ST Descriptor Status Interface
4.1.7.2. Avalon -ST Descriptor Status Sources
4.1.8. Descriptor Controller Interfaces when Instantiated Internally
4.1.8.1. Read Descriptor Controller Avalon-MM Master interface
4.1.8.2. Write Descriptor Controller Avalon-MM Master Interface
4.1.8.3. Read Descriptor Table Avalon-MM Slave Interface
4.1.8.4. Write Descriptor Table Avalon-MM Slave Interface
4.2. Clock Signals
4.3. Reset, Status, and Link Training Signals
4.4. MSI Interrupts for Endpoints
4.5. Physical Layer Interface Signals
4.5.1. Transceiver Reconfiguration
4.5.2. Serial Data Signals
4.5.2.1. Physical Layout of Hard IP In Arria V GX/GX/SX/ST Devices
4.5.2.2. Channel Placement in Arria V Devices
4.5.2.3. Physical Layout of Hard IP in Cyclone V Devices
4.5.2.4. Channel Placement in Cyclone V Devices
4.5.2.5. Physical Layout of Hard IP in Arria V GZ Devices
4.5.2.6. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
4.5.2.7. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
4.5.3. PIPE Interface Signals
4.6. Test Signals
5. Registers
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability
5.6.1. Uncorrectable Internal Error Mask Register
5.6.2. Uncorrectable Internal Error Status Register
5.6.3. Correctable Internal Error Mask Register
5.6.4. Correctable Internal Error Status Register
5.7. DMA Descriptor Controller Registers
5.7.1. Read DMA Descriptor Controller Registers
5.7.2. Write DMA Descriptor Controller Registers
5.7.3. Read DMA and Write DMA Descriptor Format
5.7.4. Read DMA Example
5.7.5. Software Program for Simultaneous Read and Write DMA
5.8. Control Register Access (CRA) Avalon-MM Slave Port
6. Reset and Clocks
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
6.2. Clocks
6.2.1. Clock Domains
6.2.1.1. pclk
6.2.1.2. coreclkout_hip
6.2.1.3. pld_clk
6.2.2. Clock Summary
7. Error Handling
7.1. Physical Layer Errors
7.2. Data Link Layer Errors
7.3. Transaction Layer Errors
7.4. Error Reporting and Data Poisoning
7.5. Uncorrectable and Correctable Error Status Bits
8. PCI Express Protocol Stack
8.1. Top-Level Interfaces
8.1.1. Avalon-MM DMA Interface
8.1.2. Clocks and Reset
8.1.3. Transceiver Reconfiguration
8.1.4. Interrupts
8.1.5. PIPE
8.2. Data Link Layer
8.3. Physical Layer
9. V-Series Avalon-MM DMA for PCI Express
9.1. Understanding the Internal DMA Descriptor Controller
9.2. Understanding the External DMA Descriptor Controller
10. Transceiver PHY IP Reconfiguration
10.1. Connecting the Transceiver Reconfiguration Controller IP Core
10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
A. Frequently Asked Questions for V-Series Avalon-MM DMA Interface for PCIe
B. V-Series Interface for PCIe Solutions User Guide Archive
C. Document Revision History
C.1. Document Revision History for the V-Series Avalon Memory Mapped (Avalon-MM) DMA Interface for PCIe Solutions User Guide

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