Intel Quartus Prime Standard Edition User Guide Power Analysis and Optimization - 2018-09-24

Version: 18.1

1. Power Analysis
1.1. Comparison of the EPE and the Intel Quartus Prime Power Analyzer
1.2. Power Estimations and Design Requirements
1.3. Power Analyzer Walkthrough
1.4. Inputs for the Power Analyzer
1.4.1. Operating Settings and Conditions
1.4.2. Sources for Signal Activity Data
1.4.2.1. Waveforms from Supported Simulators
1.4.2.2. .vcd Files from Third-Party Simulation Tools
1.4.2.2.1. Generating a .vcd in a EDA Simulation Tool
1.4.2.2.2. Generating a .vcd from ModelSim Software
1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.4.2.3.1. RTL Simulation Limitation
1.4.2.4. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.4.2.5. Signal Activities from User Defaults Only
1.5. Power Analysis in Modular Design Flows
1.5.1. Complete Design Simulation
1.5.2. Modular Design Simulation
1.5.3. Multiple Simulations on the Same Entity
1.5.4. Overlapping Simulations
1.5.5. Partial Simulations
1.5.5.1. Specifying Start and End Time when Performing Signal-Activity Calculations using the Limit VCD Period Option
1.5.6. Node Name Matching Considerations
1.5.7. Glitch Filtering
1.5.7.1. Enabling Tool Based Glitch Filtering
1.5.7.2. Enabling Glitch Filtering During Power Analysis
1.5.8. Node and Entity Assignments
1.5.8.1. Timing Assignments to Clock Nodes
1.5.9. Default Toggle Rate Assignment
1.5.10. Vectorless Estimation
1.6. Power Analyzer Compilation Report
1.7. Scripting Support
1.7.1. Running the Power Analyzer from the Command–Line
1.8. Power Analysis Revision History
2. Power Optimization
2.1. Factors Affecting Power Consumption
2.1.1. Design Activity and Power Analysis
2.1.2. Device Selection
2.1.3. Environmental Conditions
2.1.4. Device Resource Usage
2.1.4.1. Number, Type, and Loading of I/O Pins
2.1.4.2. Number and Type of Hard Logic Blocks
2.1.4.3. Number and Type of Global Signals
2.1.5. Signal Activity
2.1.5.1. Toggle Rate
2.1.5.2. Static Probability
2.2. Power Dissipation
2.3. Design Space Explorer II for Power-Driven Optimization
2.4. Power-Driven Compilation
2.4.1. Power-Driven Synthesis
2.4.1.1. Memory Block Optimization
2.4.1.2. Power-Aware Logic Mapping
2.4.1.3. Power-Aware Memory Balancing
2.4.2. Power-Driven Fitter
2.4.3. Area-Driven Synthesis
2.4.4. Gate-Level Register Retiming
2.4.5. Intel Quartus Prime Compiler Settings
2.4.6. Assignment Editor Options
2.5. Design Guidelines
2.5.1. Clock Power Management
2.5.1.1. Clock Enable in Memory Blocks
2.5.1.1.1. Memory Power Reduction Example
2.5.1.2. LAB Clock Power
2.5.1.2.1. LAB-Wide Clock Enable Example
2.5.1.3. Clock Enables
2.5.1.4. Global Signals
2.5.1.4.1. Viewing Clock Details in the Chip Planner
2.5.1.5. Merge Clocks
2.5.2. Pipelining and Retiming
2.5.3. Architectural Optimization
2.5.4. I/O Power Guidelines
2.5.5. Memory Optimization (M20K/MLAB)
2.5.5.1. Implementation
2.5.5.2. Rd/Wr Enables
2.5.6. DDR Memory Controller Settings
2.5.7. DSP Implementation
2.5.8. Reducing High-Speed Tile (HST) Usage
2.5.9. Unused Transceiver Channels
2.5.10. Periphery Power reduction XCVR Settings
2.5.10.1. Transceiver Settings
2.5.10.2. I/O Current Strength
2.6. Power Optimization Advisor
2.6.1. Set Realistic Timing Constraints
2.6.1.1. Find Timing Information
2.6.2. Appropriate Device Family
2.6.3. Dynamic Power
2.6.4. Static Power
2.6.5. Appropriate I/O Standards
2.6.6. Use RAM Blocks
2.6.7. Shut Down RAM Blocks
2.6.8. Clock Enables on Logic
2.6.9. Pipeline Logic to Reduce Glitching
2.7. Power Optimization Revision History
A. Intel Quartus Prime Standard Edition User Guides

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