Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide - Hard IP for PCI Express Endpoint and Root Port, Gen1, Gen2, Gen3 - 2016-05-02

Version: 16.0

1. Datasheet
1.1. Stratix V Avalon-ST Interface with SR-IOV for PCIe Datasheet
1.1.1. SR-IOV Features
1.2. Release Information
1.3. Device Family Support
1.4. Design Examples for SR-IOV
1.5. Debug Features
1.6. IP Core Verification
1.6.1. Compatibility Testing Environment
1.7. Performance and Resource Utilization
1.8. Recommended Speed Grades for SR-IOV Interface
1.9. Creating a Design for PCI Express
2. Getting Started with the SR-IOV DMA Example Design
2.1. Generating the Example Design Testbench
2.2. Understanding the Generated Files and Directories
2.3. Simulating the SR-IOV Example Design
2.4. Running a Gate-Level Simulation
2.5. Understanding the DMA Functionality
2.6. Compiling the Example Design with the Quartus Prime Software
2.7. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Parameter Settings
3.1. System Settings
3.2. SR-IOV System Settings
3.3. Base Address Register (BAR) Settings
3.4. SR-IOV Device Identification Registers
3.5. Interrupt Capabilities
3.6. PCI Express and PCI Capabilities Parameters
3.6.1. Device Capabilities
3.6.2. Error Reporting
3.6.3. Link Capabilities
3.6.4. Slot Capabilities
3.6.5. Power Management
3.7. PHY Characteristics
3.8. Simulation Options
4. Interfaces and Signal Descriptions
4.1. Avalon-ST TX Interface
4.2. Component-Specific Avalon-ST Interface Signals
4.3. Avalon-ST RX Interface
4.4. BAR Hit Signals
4.5. Configuration Status Interface
4.6. Clock Signals
4.7. Function-Level Reset Interface
4.8. Interrupt Interface
4.9. Configuration Extension Bus (CEB) Interface
4.9.1. Vital Product Data (VPD) Capability
4.9.1.1. Determine the Pointer Address of an External Capability Register
4.9.1.2. VPD Capability Implementation
4.10. Implementing MSI-X Interrupts
4.11. Local Management Interface (LMI) Signals
4.12. Reset, Status, and Link Training Signals
4.13. Transceiver Reconfiguration
4.14. Serial Data Signals
4.14.1. Physical Layout of Hard IP In Stratix V Devices
4.14.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
4.15. Test Signals
4.16. PIPE Interface Signals
5. Registers
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. PCI and PCI Express Configuration Space Registers
5.2.1. Type 0 Configuration Space Registers
5.2.2. PCI and PCI Express Configuration Space Register Content
5.2.3. Interrupt Line and Interrupt Pin Register
5.3. MSI Registers
5.4. MSI-X Capability Structure
5.5. Power Management Capability Structure
5.6. PCI Express Capability Structure
5.7. Advanced Error Reporting (AER) Enhanced Capability Header Register
5.8. Uncorrectable Error Status Register
5.9. Uncorrectable Error Mask Register
5.10. Uncorrectable Error Severity Register
5.11. Correctable Error Status Register
5.12. Correctable Error Mask Register
5.13. Advanced Error Capabilities and Control Register
5.14. Header Log Registers 0-3
5.15. SR-IOV Virtualization Extended Capabilities Registers
5.15.1. SR-IOV Virtualization Extended Capabilities Registers Address Map
5.15.2. ARI Enhanced Capability Header
5.15.3. SR-IOV Enhanced Capability Registers
5.15.4. Initial VFs and Total VFs Registers
5.15.5. VF Device ID Register
5.15.6. Page Size Registers
5.15.7. VF Base Address Registers (BARs) 0-5
5.15.8. Secondary PCI Express Extended Capability Header
5.15.9. Lane Status Registers
5.16. Virtual Function Registers
6. Reset and Clocks
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
6.2. Function Level Reset (FLR)
6.3. Clocks
6.3.1. Clock Domains
6.3.1.1. pclk
6.3.1.2. coreclkout_hip
6.3.1.3. pld_clk
6.3.2. Clock Summary
7. Programming and Testing SR-IOV Bridge MSI Interrupts
7.1. Setting Up and Verifying MSI Interrupts
7.2. Masking MSI Interrupts
7.3. Dropping a Pending MSI Interrupt
8. Error Handling
8.1. Physical Layer Errors
8.2. Data Link Layer Errors
8.3. Transaction Layer Errors
8.4. Error Reporting and Data Poisoning
8.5. Uncorrectable and Correctable Error Status Bits
9. IP Core Architecture
9.1. Data Link Layer
9.2. Physical Layer
9.3. Top-Level Interfaces
9.3.1. Avalon-ST Interface
9.3.2. Clocks and Reset
9.3.3. Transceiver Reconfiguration
9.3.4. Interrupts
9.3.5. PIPE
9.4. Physical and Virtual Function Address Assignments
9.5. Stratix V Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
10. Design Implementation
10.1. Making Analog QSF Assignments Using the Assignment Editor
10.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins
10.3. Recommended Reset Sequence to Avoid Link Training Issues
10.4. SDC Timing Constraints
11. Transceiver PHY IP Reconfiguration
11.1. Connecting the Transceiver Reconfiguration Controller IP Core
11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging
12.1. Setting Up Simulation
12.1.1. Changing Between Serial and PIPE Simulation
12.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants
12.1.3. Viewing the Important PIPE Interface Signals
12.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
12.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
12.1.6. Changing between the Hard and Soft Reset Controller
12.2. Hardware Bring-Up Issues
12.3. Link Training
12.3.1. Debugging Link that Fails To Reach L0
12.4. Use Third-Party PCIe Analyzer
12.5. BIOS Enumeration Issues
A. Frequently Asked Questions for PCI Express
B. Transaction Layer Packet (TLP) Header Formats
B.1. TLP Packet Formats without Data Payload
B.2. TLP Packet Formats with Data Payload
C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
13. Document Revision History
13.1. Document Revision History for the Intel Arria 10 Avalon Streaming with SR-IOV IP for PCIe User Guide

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