External Memory Interface - Cyclone 10 GX devices offer external memory bandwidth of up to 1×72-bit or 2×40-bit DDR3 memory interfaces running at up to 1,866 Mbps. This bandwidth provides ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers.

Cyclone^® 10 GX devices offer external memory bandwidth of up to 1×72-bit or 2×40-bit DDR3 memory interfaces running at up to 1,866 Mbps. This bandwidth provides ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers.

The memory interface within Cyclone^® 10 GX FPGAs delivers the highest performance and ease of use. You can configure up to a maximum width of 72 bits when using the hard memory controllers.

Each I/O contains a hardened DDR read/write path (PHY) capable of performing key memory interface functionality such as read/write leveling, FIFO buffering to lower latency and improve margin, timing calibration, and on-chip termination.

The timing calibration is aided by the inclusion of hard microcontroller based on Altera's Nios^® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Cyclone^® 10 GX device to compensate for any changes in process, voltage, or temperature either within the Cyclone^® 10 GX device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.