Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Errata - 2018-12-04

Intel Acceleration Stack for Intel Xeon CPU with FPGAs Version 1.2 Errata
Flash Fallback Does Not Meet PCIe Timeout
Unsupported Transaction Layer Packet Types
fpgainfo errors -c Does Not Clear the Error Response When Non-Fatal Errors Occur
Board management controller does not verify the CRC in a PLDM request.
The 1.2 V current and 1.8 V voltage upper non-recoverable (UNR) limits for the board management controller and the pacd are set to the same value.
Intel Acceleration Stack for Intel Xeon CPU with FPGAs v1.2 Errata Revision History

Back to home page