The I/O banks of the
Agilex™ 7 FPGAs and SoCs contain I/O PLLs for use in I/O interfacing or
fabric clocking.
| Series | I/O Bank I/O PLL | Fabric-Feeding I/O PLL |
|---|---|---|
| F-Series | 2 | 1 |
| I-Series | 2 | 1 |
| M-Series | 2 | 1 |
You can use the I/O PLLs for general purpose applications in the core fabric, such as clock network delay compensation and zero-delay clock buffering.
The I/O PLLs are situated adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O bank. This placement creates a tight coupling of the PLLs with the I/Os that need them. The architecture simplifies designing external memory and high-speed LVDS interfaces, and eases timing closure.