11. Hard Processor System in Agilex™ 7 SoCs - The Agilex 7 SoCs hard processor system (HPS) consists of multicore Arm processors. Additionally, the HPS adds a system memory management unit that enables system-wide hardware virtualization. - 2026-03-07

Agilex™ 7 FPGAs and SoCs Device Overview
The Agilex™ 7 SoCs hard processor system (HPS) consists of multicore Arm® processors. Additionally, the HPS adds a system memory management unit that enables system-wide hardware virtualization.

With the HPS architecture improvements, the Agilex™ 7 SoCs fulfill the requirements of current and future embedded markets, including:

  • Wireless and wireline communications
  • Datacenter acceleration
  • Numerous military applications
  • Various industrial applications

The HPS of the F-Series, I-Series, and M-Series SoCs consists a quad-core Arm® Cortex® -A53, allowing you to easily migrate existing SoC designs from Stratix® 10 SoCs.

Figure 13.  Agilex™ 7 SoCs HPS Block Diagram


Table 27.  Summary of Agilex™ 7 SoCs Key Features
Feature Description
Processor units
  • Quad-core Arm® Cortex® -A53 MPCore processor unit
    • CPU frequency up to 1.5 GHz
      • 2.3 MIPS/MHz instruction efficiency
      • At 1.5 GHz, total performance of 13,800 MIPS
    • Arm® v8-A architecture
  • Run 64-bit and 32-bit Arm® instructions
  • 16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
  • Arm® Jazelle® runtime compilation target (RCT) execution architecture with 8-bit Java® bytecodes
  • Superscalar, variable-length, out-of-order pipeline with dynamic branch prediction
  • Improved Arm® Neon™ media processing engine
  • Single-precision and double-precision floating-point unit
  • Arm® CoreSight™ debug and trace technology
System memory management unit
  • Enables a unified memory model
  • Extends hardware virtualization into peripherals implemented in the FPGA fabric
Cache coherency unit Propagates changes in shared data stored in cache throughout the system to provide I/O coherency for co-processing elements
Cache memory
  • L1 cache:
    • 32 KB L1 I-cache with parity check
    • 32 KB of L1 D-cache with ECC
    • Parity checking
  • L2 cache:
    • Shared 1 MB
    • 8-way set associative
    • SEU protection with parity on TAG ram and ECC on data RAM
    • Cache lockdown support
On-chip memory 256 KB on-chip RAM
External SDRAM and flash memory Interfaces for HPS Hard memory controller
  • Supports DDR4, up to 3200 Mbps
  • 40-bit (32-bit + 8-bit ECC)
  • Some packages support 72-bit (64 bit + 8 bit ECC)
  • ECC support including calculation, error correction, write-back correction, and error counters
  • Software-configurable priority scheduling on individual SDRAM bursts
  • Fully programmable timing parameter support for all JEDEC® -specified timing parameters
  • Multi-port front end (MPFE) interface to the hard memory controller, supporting AMBA® 4 AXI QoS for interface to the FPGA fabric
NAND flash controller
  • Integrated descriptor-based controller with DMA
  • Programmable hardware ECC support
  • Support for 8-bit and 16-bit flash devices
  • Supports the ONFI 1.0 specification
SD/SDIO/MMC controller
  • Integrated descriptor-based DMA controller
  • Supports CE-ATA digital commands
  • Supports eMMC version 5.0
  • 50 MHz operating frequency
DMA controller
  • Eight channels
  • Supports up to 32 peripheral handshake interfaces
Communication interface controllers Ethernet MAC
  • Three Ethernet MACs supporting 10 Mbps, 100 Mbps, and 1 Gbps with integrated DMA
  • Ethernet standards:
    • IEEE 1588-2002 and IEEE 1588-2008 standards for precise networked clock synchronization
    • IEEE 802.1Q VLAN tag detection for reception frames
  • Ethernet interfaces:
    • Supports RGMII and RMII external PHY Interfaces
    • Supports MII and GMII operating modes through standard FPGA I/O
    • Supports RMII operating mode using MII to RMII adapter
    • Supports RGMII operating mode using GMII to RGMII adapter
    • Supports SGMII operating mode using GMII to SGMII adapter
USB 2.0 OTG
  • Two USB OTG controllers with DMA
  • Dual-role device (device and host functions)
    • High-speed (480 Mbps)
    • Full-speed (12 Mbps)
    • Low-speed (1.5 Mbps)
    • Supports USB 1.1 (full-speed and low-speed)
  • Integrated descriptor-based scatter-gather DMA
  • Support for external ULPI PHY
  • Up to 16 bidirectional endpoints, including control endpoint
  • Up to 16 host channels
  • Supports generic root hub
  • Configurable to USB OTG 1.3 and USB OTG 2.0 modes
I2C
  • Five I2C controllers, three can be used by the Ethernet MAC for MIO to external PHY
  • Support 100 Kbps and 400 Kbps modes
  • Support 7-bit and 10-bit addressing modes
  • Support master and slave operating modes
UART
  • Two UART 16550-compatible controllers
  • Programmable baud rate up to 115.2 kilobaud
SPI
  • Four SPI (two masters, two slaves)
  • Supports full duplex and half duplex
Timers
  • Four general-purpose timers
  • Four watchdog timers
I/O
  • 48 HPS direct I/Os allow HPS peripherals to connect directly to the I/Os
  • Up to two FPGA fabric I/O banks assignable to the HPS for HPS DDR access
Interconnect to logic core HPS–to–FPGA bridge
  • Allows HPS bus masters to access bus slaves in FPGA fabric
  • Configurable 32-, 64-, or 128-bit AMBA® AXI data interface allows high-bandwidth HPS master transactions to FPGA fabric
HPS–to–SDM and SDM–to–HPS bridges Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS
Lightweight HPS–to–FPGA bridge Lightweight 32-bit AMBA® AXI interface suitable for low bandwidth register access from HPS to soft peripherals in the FPGA fabric
FPGA–to–HPS bridge
  • Configurable 128, 256, or 512 bits ACE-Lite interface
  • Up to 256-bit FPGA–to–HPS interface targeting the HPS
  • Up to 512-bit FPGA–to–HPS interface targeting the DDR