8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs - The Agilex 7 FPGAs and SoCs are equipped with general purpose I/Os (GPIO) that support various I/O standards from 1.05 V to 1.5 V . - 2025-12-16

Agilex™ 7 FPGAs and SoCs Device Overview
The Agilex™ 7 FPGAs and SoCs are equipped with general purpose I/Os (GPIO) that support various I/O standards from 1.05 V to 1.5 V.

In each GPIO bank, there are two 48-pin sub-banks, providing a total of 96 pins per bank. In the M-Series FPGAs, each sub-bank has its own VCCIO.

Table 22.  I/O Standards Support and Performance in Agilex™ 7 FPGAs and SoCs
I/O Standard Series Specification Notes
LVCMOS/LVTTL

F-Series

I-Series

 1.2 V single-ended —

M-Series

 1.05 V, 1.1 V, and 1.2 V single-ended

TDS

(LVDS compatible)

F-Series

I-Series
  • 1.5 V
  • Up to 1.6 Gbps
Works with the LVDS SERDES IP

M-Series
  • 1.3 V
  • Up to 1.6 Gbps