15. Configuration via Protocol Using PCIe for Agilex™ 7 FPGAs and SoCs - Configuration via protocol (CvP) using PCIe allows you to configure the Agilex 7 FPGAs and SoCs across the PCIe bus. This capability simplifies board layout and increases system integration. - 2025-12-16

The embedded PCIe^® hard IP operates in autonomous mode before the FPGA is configured. Using this hard IP, you can power up and activate the PCIe^® bus within the 100 ms time allowed by the PCIe^® specification.

The Agilex™ 7 FPGAs and SoCs also support partial reconfiguration across the PCIe^® bus. This capability reduces system downtime by keeping the PCIe^® link active during device reconfiguration.