The
Agilex™ 7 FPGAs and SoCs use an enhanced adaptive logic module (ALM) similar to the previous generation FPGAs such as
the
Arria® 10 and
Stratix® 10 FPGAs. The enhanced ALM allows for efficient implementation of logic functions and
easy IP conversion between
Agilex™ 7 FPGAs and
Arria® 10 and
Stratix® 10 FPGAs.
Figure 6. ALM Block DiagramThis figure shows the ALM with 8-input fracturable look-up table
(LUT), two dedicated embedded adders, and four dedicated registers.
| Key Feature | Capability |
|---|---|
| High register count | Together with the second generation Hyperflex® architecture, the four registers per 8-input fracturable LUT enables maximized core performance at very high core logic utilization. |
| ALM operating modes | Optimize core logic utilization by implementing an extended 7-input logic function, a single 6-input logic function, or two smaller independent functions (for example, two 4-input functions). |
| Two clock sources | Two clock sources per ALM generate two normal clocks and two delayed clocks to drive the ALM registers, resulting in more clock domains and time-borrowing capability. |
| Additional LUT outputs | Additional fast 6-LUT and 5-LUT outputs for combinatorial functions improve critical path for logic cascade. |
| Improved register packing | The improved register packing, including 5-input LUT with two packed register paths, results in more efficient usage of the fabric area and improved critical path. |
| Latch mode support | The ALM supports latch mode in the address latch enable. |
The Quartus® Prime software capitalizes on the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Quartus® Prime software simplifies design reuse as the software automatically maps legacy designs into the ALM architecture of the Agilex™ 7 FPGAs and SoCs.