8. Synthesize your Component IP with Quartus Prime Pro Edition - When you are satisfied with the predicted performance of your component, use Quartus Prime Pro Edition to synthesize your component. Synthesis also generates accurate area and performance (f MAX ) estimates for your design, however your design is not expected to cleanly close timing in the Quartus Prime reports.

When you are satisfied with the predicted performance of your component, use Quartus^® Prime Pro Edition to synthesize your component. Synthesis also generates accurate area and performance (f_MAX) estimates for your design, however your design is not expected to cleanly close timing in the Quartus^® Prime reports.

You can expect to see timing closure warnings in the Quartus^® Prime logs because the generated project in the Intel^® HLS Compiler quartus folder targets a clock speed of 1000 MHz to achieve the best possible placement for your design. The f_MAX value presented in the High-Level Design Reports is an estimate of the maximum clock rate that your component can cleanly close timing for.

After the Quartus^® Prime compilation completes, the Summary report of the High-Level Design Reports show the area and performance data for your components. These estimates are more accurate than estimates generated when you compile your component with the Intel^® HLS Compiler Pro Edition.

Typically, Quartus^® Prime compilation times can take minutes to hours depending on the size and complexity of your components.

To synthesize your component IP and generate quality of results (QoR) data, do one of the following actions:

Instruct the HLS compiler to run the Quartus^® Prime compilation flow automatically after synthesizing the components. Include the --quartus-compile option in your i++ command.
```
i++ -march="<FPGA_family_or_part_number>" --quartus-compile ...
```
If you are trying to get an accurate estimate of the f_MAX range of your component, use the --quartus-seed option to automate seed sweeps:
```
i++ -march="<FPGA_family_or_part_number>" --quartus-compile --quartus-seed <seed> ...
```
Tip: For the best estimates, run the command multiple times, each with a different seed number.
If you already have the RTL for your component synthesized, you can navigate to the quartus directory and compile the Quartus^® Prime project by invoking the following command:
```
quartus_sh --flow compile quartus_compile
```
Tip: Add the path to quartus_sh (Linux) or quartus_sh.exe (Windows) to your PATH environment variable.