A. Reviewing the High-Level Design Reports (report.html) - To launch the High-Level Design Reports, open the following file in a web browser: <result> .prj/reports/report.html . - 2025-12-15

Altera High Level Synthesis Compiler Pro Edition User Guide
Version
24.1
Product Type
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software > Pro Edition
Device Families > Arria Families > Arria 10
Device Families > Agilex Families
Device Families > Agilex Families > Agilex 7 > F-Series
Device Families > Stratix Families > Stratix 10
Development Software and Tools > FPGA Design & Simulation Tools > Quartus Prime Design Software
Device Families > Agilex Families > Agilex 7
Device Families > Cyclone Families
Device Families > Arria Families
Device Families > Stratix Families
Device Families > Cyclone Families > Cyclone V
Device Families > Agilex Families > Agilex 7 > I-Series
Device Families > Cyclone Families > Cyclone 10 > Cyclone 10 GX
Device Families > Cyclone Families > Cyclone 10
Resource Type
Documentation > User Guides
ft:sourceName
DITA
After compiling your component, the Intel® HLS Compiler generates a group of reports and viewers that helps you analyze various component aspects, such as area, loop structure, memory usage, and component pipeline. To launch the High-Level Design Reports, open the following file in a web browser: <result>.prj/reports/report.html.