3.1. High Level Synthesis Design Flow - The Intel High Level Synthesis (HLS) Compiler helps speed your IP development by letting you compile your IP component C++ code to different targets, depending on where you are in your IP development cycle. - 2025-12-15

Altera High Level Synthesis Compiler Pro Edition User Guide
Version
24.1
The Intel® High Level Synthesis (HLS) Compiler helps speed your IP development by letting you compile your IP component C++ code to different targets, depending on where you are in your IP development cycle.
The typical design flow when you use the Intel® HLS Compiler Pro Edition consists of the following stages:
  1. Creating your component and testbench.

    You can write a complete C++ application that contains both your component code and your testbench code.

    For details, see Creating a High-Level Synthesis Component and Testbench .

  2. Verify the functionality of your component algorithm and testbench.

    Verify the functionality by compiling your design to an x86-64 executable and running the executable. For details, see Verifying the Functionality of Your Design .

  3. Optimize and refine the FPGA performance of your component.

    Optimize the FPGA performance of your component by compiling your design to an FPGA target and reviewing the high-level design report to see where you can optimize your component. This step generates RTL code for your component. For details, see Optimizing and Refining Your Component .

    After initial optimizations, you can see where to further refine your component by simulating it. For details, see Verifying Your IP with Simulation .

  4. Synthesize your component with Quartus® Prime.

    For details, see Synthesize your Component IP with Quartus Prime Pro Edition .

    Synthesizing your component generates accurate quality-of-results (QoR) metrics like FPGA area utilization and fMAX.

  5. Integrate your IP into a system with Quartus® Prime or Platform Designer (formerly Qsys).

    For details, see Integrating your IP into a System.

The following flowchart shows a coarse-grained progression through the stages of a typical Intel® High Level Synthesis (HLS) Compiler design flow.
Figure 1. Overview of Procedure for Synthesizing IP for Intel® FPGA Products

For an example of the Intel® HLS Compiler design flow, watch the HLS Walkthrough series at the Intel FPGA channel on YouTube or complete the full-design tutorial found in <quartus_installdir>/hls/examples/tutorials/usability.

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