7.1. Generation of the Verification Testbench Executable - When you include -march=" <FPGA_family_or_part_number> " in your i++ command, the HLS compiler identifies the components and performs high-level synthesis on them. It then generates an executable to run a verification testbench. - 2025-12-15

Altera High Level Synthesis Compiler Pro Edition User Guide
Version
24.1
When you include -march="<FPGA_family_or_part_number>" in your i++ command, the HLS compiler identifies the components and performs high-level synthesis on them. It then generates an executable to run a verification testbench.
The HLS compiler performs the following tasks to generate the verification executable:
  1. Parses your design, and extracts the functions and symbols necessary for component synthesis to the FPGA. The HLS compiler also extracts the functions and symbols necessary for compiling the C++ testbench.
  2. Compiles the testbench code to generate an x86-64 executable that also runs the simulator.
  3. Compiles the code for component synthesis to the FPGA. This compilation generates RTL for the component and an interface to the x86-64 executable testbench.