D. Document Revision History for Intel HLS Compiler Pro Edition User Guide - 2025-12-15

Altera High Level Synthesis Compiler Pro Edition User Guide

Version: 24.1

Document Version	Intel^® HLS Compiler Pro Edition Version	Changes
2025.01.23	–	Updated for the discontinuance of the Intel^® HLS Compiler.
2024.04.01	24.1	Maintenance release. Updated `<quartus_installdir>` path information for Version 24.1.
2023.12.04	23.4	Maintenance release. Updated `<quartus_installdir>` path information for Version 23.4.
2023.10.02	23.3	Maintenance release. Updated `<quartus_installdir>` path information for Version 23.3.
2023.06.26	23.2	Maintenance release. Updated `<quartus_installdir>` path information for Version 23.2.
2023.04.03	23.1	Updated `<quartus_installdir>` path information for Version 23.1. Updated product family name to "Intel Agilex 7."
2022.12.19	22.4	Added pending deprecation notice. Updated `<quartus_installdir>` path information for Version 22.4.
2022.09.23	22.3	Maintenance release. Updated `<quartus_installdir>` path information for Version 22.3.
2022.06.20	22.2	Maintenance release. Updated `<quartus_installdir>` path information for Version 22.2.
2022.03.28	22.1	Maintenance release. Updated `<quartus_installdir>` path information for Version 22.1.
2021.12.13	21.4	Added references to the full-design tutorial and HLS Walkthrough video series to High Level Synthesis Design Flow .
2021.10.04	21.3	Replaced references to Mentor^® ModelSim^® with Siemens^® EDA Questa^®.
2021.06.21	21.2	Revised references to Avalon Interfaces to align with new Avalon Interconnect terminology. Avalon master interfaces are now Avalon host interfaces, and Avalon slave interfaces are now Avalon agent interfaces.
2021.03.29	21.1	Revised Schedule Viewer (Beta) to include information about new dependency lines shown in the viewer. Updated The High-Level Design Reports , to reflect the changed top-level menu names and ordering.
2020.12.14	20.4	Revised Verifying the Functionality of Your Design to add details about how to verify your design functionality through emulation. Revised Verifying Your IP with Simulation to add details about how to verify your design functionality through simulation. Updated Reviewing Cluster Information with a link to more information about clusters in the Intel^® HLS Compiler Pro Edition Best Practices Guide. Revised System Viewer with a link to more information about clusters in the Intel^® HLS Compiler Pro Edition Best Practices Guide. Moved the descriptions of blocks shown in the Graph Viewer from System Viewer to Reviewing Function Information . Moved information from the Scheduled f _MAX description in Loop Analysis Report into the following topics in the Intel^® HLS Compiler Pro Edition Best Practices Guide: Maximum Frequency (f_MAX) Balancing Target f_MAX and Target II
2020.08.28	20.3	Added information about the Loop Viewer to Loops Viewer (Alpha) . Renamed Reviewing Loop Information. The topic is now titled Loop Analysis Report . Added information about the Loop Analysis Report Bottlenecks pane to Loop Analysis Report . Updated Debugging during Verification with information about the `-ghdl=<depth>` option. Revised the code example and images in Avalon MM Host Interfaces. This section is part of Reviewing Component Interfaces . Renamed Reviewing Your Component Verification Results. The topic is now titled Verification Statistics Report . Removed references to the f_MAX II Report. The report is removed from Intel^® HLS Compiler Pro Edition Version 20.3.
2020.06.22	20.2	Added information about compiler-generated short names to Integrating your IP into a System.
2020.04.14	20.1	Made some minor revisions to Overview of the Intel High Level Synthesis (HLS) Compiler Pro Edition . Added a restriction on loops to Intel HLS Compiler Pro Edition Restrictions . Removed Reviewing f_MAX II Information. This information is now part of Reviewing Loop Information .
2019.12.16	19.4	Removed information about Intel^® HLS Compiler Standard Edition. For the Intel^® HLS Compiler Standard Edition information, see Intel^® HLS Compiler Standard Edition User Guide. Renamed Viewing Component Design to Reviewing Component Architecture . Moved description of component and task representation in the High-Level Design reports from Reviewing Component Architecture to System Viewer .

Document Revision History for Intel^® HLS Compiler User Guide

Previous versions of the Intel^® HLS Compiler User Guide contained information for both Intel^® HLS Compiler Standard Edition and Intel^® HLS Compiler Pro Edition.

Document Version	Quartus^® Prime Version	Changes
2019.09.30	19.3	Added System Viewer . Split information about viewing your component design into separate sections for Intel^® HLS Compiler Pro Edition and Intel^® HLS Compiler Standard Edition: Reviewing Component Architecture Viewing Component Design In Verifying the Functionality of Your Design , removed information about using MSVC to debug a design compiled with the i++ command. You cannot use MSVC to debug a design compiled with the i++ command. On Linux, you can use GDB to debug a design compiled with the i++ command.
2019.07.01	19.2	Updated Reviewing the High-Level Design Reports (report.html) to reflect the merging of various viewers into the Graph Viewer (beta). Some images in the section do not reflect the new reporting interface. The images will be updated in a future release of this document.
2019.04.01	19.1	Updated Reviewing the High-Level Design Reports (report.html) section as follows: The Function Viewer report is the new name for what previously called the Component Viewer report. Added Function Memory Viewer . The Function Memory Viewer report replaces the Component Memory Viewer report. Added Reviewing System Information Added Reviewing Block Information Added Reviewing Cluster Information Updated to Synthesize your Component IP with Quartus Prime Pro Edition to indicated that compiling your component with Quartus^® Prime is not intended to close timing for your component. Revised the Intel HLS Compiler Pro Edition Restrictions as follows: Revised C++ 14 restriction Removed Overloading/Templates limitation Added Reviewing f_MAX II Information.
2019.01.03	18.1.1	Fixed typos in table headings in Intel HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros . Corrected typos in High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls and Comparison of Explicit and Enqueued Function Calls : `ihs_hls_component_run_all` is now `ihc_hls_component_run_all`. `ihs_hls_enqueue` is now `ihc_hls_enqueue`.
2018.12.24	18.1.1	Added information about `HLS_SYNTHESIS` preprocessor macro to Intel HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros .
2018.09.24	18.1	The Intel^® HLS Compiler has a new front end. For a summary of the changes introduced by this new front end, see Improved Intel HLS Compiler Front End in the Intel^® High Level Synthesis Compiler Version 18.1 Release Notes. In Debugging during Verification , added a reminder to run the executable compiled with the -ghdl option before viewing the waveform in ModelSim^® . Added information to Overview of the Intel High Level Synthesis (HLS) Compiler Pro Edition topic to indicate that the Intel^® HLS Compiler treats all input file as C++14-compliant code. While you can compile code compliant with other standards by using the `-std` compile option, not all Intel^® HLS Compiler features are supported for other C++ standards.
2018.07.02	18.0	Added information about viewing the high level design report data in JSON files. See Accessing HLD FPGA Reports in JSON Format for details. Added related links to Verifying Your IP with Simulation for Mentor Graphics^® ModelSim^® prerequisites.
2018.05.07	18.0	Starting with Quartus^® Prime Version 18.0, the features and devices supported by the Intel^® HLS Compiler depend on what edition of Quartus^® Prime you have. Intel^® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows: Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Quartus^® Prime Pro Edition. Indicates that a feature or content applies only to the Intel^® HLS Compiler provided with Quartus^® Prime Standard Edition. Added important prerequisite for MAX^® 10 users to Synthesize your Component IP with Quartus^® Prime Standard Edition . Revised Debugging during Verification to clarify how to view the waveform in ModelSim^® after simulation.
2017.12.22	17.1.1	Corrected typos in Execution Model : `ihs_hls_component_run_all` is now `ihc_hls_component_run_all`. `ihs_hls_run_all_enqueued` is now `ihc_hls_component_run_all`.
2017.11.06	17.1	Moved the following content to Intel High Level Synthesis Compiler Pro Edition Best Practices Guide: Moved compiler best practice content from "Creating a High-Level Synthesis Component and Testbench " to "Best Practices for Coding and Compiling Your Component". Moved the following content to Intel High Level Synthesis Compiler Reference Manual" Moved "High Level Synthesis Component Interface Definition" to Component Interface Definition. Moved Reset Behavior section to "Reset Behavior". Added new chapter "Optimizing and Refining Your Component " to provide a brief introduction to the high-level design report (report.html). Added new chapter "Verifying the Functionality of Your Design " to provide some details about how to perform functional verification on your HLS component. Rearranged the order of sections to better reflect the user flow of using the compiler.
2017.06.23	—	Minor changes and corrections.
2017.06.09	—	Updated Intel HLS Compiler Pro Edition Restrictions to add, remove, and change compiler limitations found in this release. Rebranding __ALTERA_COMPILER__ and __ALTERA_TYPE__ to __INTELFPGA_COMPILER__ and __INTELFPGA_TYPE__ Changed references for the compiler option `-march=fpga` to `-march="<FPGA_family_or_part_number>"`. For details about changes to the `-march` compiler option, see Command Options that Customize Compilation in the Intel^® HLS Compiler Pro Edition Reference Manual Added recommendation to compile components with `-Wconversion` to Creating a High-Level Synthesis Component and Testbench . Added information about HLS component reset behavior in Reset Behavior.
2017.02.03	—	Added note about what functions have components synthesized for them when you run the `i++` command. Under Reviewing Your Component's report.html File, added Component memory viewer section to introduce the Component memory viewer report. Under Reviewing Your Component's report.html File, updated examples and screen captures to reflect examples and tutorials provided with the Intel^® HLS Compiler. Updated the values for the `__ALTERA_COMPILER__` HLS compiler-defined preprocessor macro.
2016.11.30	—	Under Reviewing Your Component's report.html File, added the Information on Component Verification Results section to introduce the Verification Statistics report. In Verifying Your HLS IP, noted that information on the supported versions of the ModelSim software is available in the Quartus^® Prime Software and Device Support Release Notes. Removed the Latency Measurement during Verification section because the APIs described within have been removed. In Adding the Compiler-Generated IP into a Quartus^® Prime Project and Adding the Compiler-Generated IP into a Qsys System, specified that the for the Quartus^® Prime Standard Edition software, the file in question is the .qsys file. For the Quartus^® Prime Pro Edition software, the file in question is the .ip file. Updated the Limitations of the HLS Compiler section: Removed the limitation on ModelSim software version support. Added the limitation that C++ library calls are not supported on Windows.
2016.09.12	—	Initial release.