By default, the HLS compiler instructs the simulator not to log any signals because logging signals slows the simulation, and the waveforms files can be very large. However, you can configure the compiler to save these waveforms for debugging purposes.
To enable signal logging in the simulator, invoke the i++ command with the -ghdl option
in your i++ command, as follows:
i++ -march="<FPGA_family_or_part_number>" -ghdl[=<depth>] <input files>Specify the <depth> attribute to specify how many levels of hierarchy are logged. Specify -ghdl=1 to log only top level signals. If you do not specify the <depth> attribute, all signals are logged.
Remember: After you compile your component and testbench with the -ghdl option, run the resulting executable to run
the simulation and generate the waveform. By default, the name of the executable
is a.out (Linux) or a.exe (Windows).
When the simulation finishes, open the vsim.wlf file inside the <result>.prj/verification directory to view the waveform.
To view the waveform after the simulation finishes: