JESD204B IP User Guide - Describes the features of the JESD204B IP and provides instructions and guidelines about how to configure and run the IP. - 2024-12-16

Version: 24.2

1. JESD204B IP Quick Reference
2. About the JESD204B IP
2.1. Release Information
2.2. Device Family Support
2.3. Datapath Modes
2.4. IP Variation
2.5. JESD204B IP Configuration
2.5.1. Run-Time Configuration
2.6. Channel Bonding
2.7. Performance and Resource Utilization
3. Getting Started
3.1. Introduction to Altera IP Cores
3.2. Installing and Licensing IPs
3.3. IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.6.1. Creating a New Quartus Prime Project
3.6.2. Parameterizing and Generating the IP
3.6.3. Compiling the JESD204B IP Core Design
3.6.4. Programming an FPGA Device
3.7. JESD204B Design Examples
3.8. JESD204B IP Design Considerations
3.8.1. Integrating the JESD204B IP in Platform Designer
3.8.2. Pin Assignments
3.8.3. Adding External Transceiver PLLs
3.8.4. Timing Constraints For Input Clocks
3.9. JESD204B IP Parameters
3.10. JESD204B IP Component Files
3.11. JESD204B IP Testbench
3.11.1. Generating and Simulating the IP Testbench
3.11.1.1. Generating the Testbench Simulation Model
3.11.1.2. Simulating the IP Testbench
3.11.2. Testbench Simulation Flow
4. JESD204B IP Functional Description
4.1. Transmitter
4.1.1. TX Data Link Layer
4.1.1.1. TX CGS
4.1.1.2. TX ILAS
4.1.1.3. User Data Phase
4.1.2. TX PHY Layer
4.2. Receiver
4.2.1. RX Data Link Layer
4.2.1.1. RX CGS
4.2.1.2. Frame Synchronization
4.2.1.3. Frame Alignment
4.2.1.4. Lane Alignment
4.2.1.5. ILAS Data
4.2.1.6. Initial Lane Synchronization
4.2.2. RX PHY Layer
4.3. Operation
4.3.1. Operating Modes
4.3.1.1. Subclass 0 Operating Mode
4.3.1.2. Subclass 1 Operating Mode
4.3.1.3. Subclass 2 Operating Mode
4.3.2. Scrambler/Descrambler
4.3.3. SYNC_N Signal
4.3.4. Link Reinitialization
4.3.5. Link Startup Sequence
4.3.6. Error Reporting Through SYNC_N Signal
4.4. Clocking Scheme
4.4.1. Device Clock
4.4.2. Link Clock
4.4.3. Local MultiFrame Clock
4.4.4. Clock Correlation
4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme
4.5.1. Reset Sequence
4.5.2. ADC–FPGA Subsystem Reset Sequence
4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals
4.6.1. Transmitter Signals
4.6.2. Receiver Signals
4.7. Registers
4.7.1. Register Access Type Convention
4.7.2. Transmitter Registers
4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines
5.1. SYSREF Guidelines
5.2. Constraining Incoming SYSREF Signal
5.3. Programmable RBD Offset
5.4. Programmable LMFC Offset
5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines
6.1. Clocking Scheme
6.2. JESD204B Parameters
6.3. SPI Programming
6.4. Converter and FPGA Operating Conditions
6.5. Signal Polarity and FPGA Pin Assignment
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
6.7. Debugging JESD204B Link Using System Console
7. JESD204B IP User Guide Archives
8. Document Revision History for the JESD204B IP User Guide

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