Arria V Device Overview - Provides an overview of the Arria V device family features, ordering codes options, maximum resource counts, and available device packages. - 2020-11-20

1. Arria V Device Overview
1.1. Key Advantages of Arria V Devices
1.2. Summary of Arria V Features
1.3. Arria V Device Variants and Packages
1.3.1. Arria V GX
1.3.1.1. Available Options
1.3.1.2. Maximum Resources
1.3.1.3. Package Plan
1.3.2. Arria V GT
1.3.2.1. Available Options
1.3.2.2. Maximum Resources
1.3.2.3. Package Plan
1.3.3. Arria V GZ
1.3.3.1. Available Options
1.3.3.2. Maximum Resources
1.3.3.3. Package Plan
1.3.4. Arria V SX
1.3.4.1. Available Options
1.3.4.2. Maximum Resources
1.3.4.3. Package Plan
1.3.5. Arria V ST
1.3.5.1. Available Options
1.3.5.2. Maximum Resources
1.3.5.3. Package Plan
1.4. I/O Vertical Migration for Arria V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.7.1. Types of Embedded Memory
1.7.2. Embedded Memory Capacity in Arria V Devices
1.7.3. Embedded Memory Configurations
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.11.1. Hard and Soft Memory Controllers
1.11.2. External Memory Performance
1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers
1.12.1. Transceiver Channels
1.12.2. PMA Features
1.12.3. PCS Features
1.13. SoC with HPS
1.13.1. HPS Features
1.13.1.1. System Peripherals and Debug Access Port
1.13.1.2. HPS–FPGA AXI Bridges
1.13.1.3. HPS SDRAM Controller Subsystem
1.13.2. FPGA Configuration and Processor Booting
1.13.3. Hardware and Software Development
1.14. Dynamic Reconfiguration
1.14.1. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History

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