The main concern in most FIFO design is the output latency of the read and write status signals.
| Output Mode | Optimization Option 27 | Output Latency (in number of clock cycles) |
|---|---|---|
| Normal 28 | Speed | wrreq / rdreq to full: 1 |
| wrreq to empty: 2 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| rdreq to q[]: 1 | ||
| Area | wrreq / rdreq to full: 1 | |
| wrreq / rdreq to empty : 1 | ||
| wrreq / rdreq to usedw[] : 1 | ||
| rdreq to q[]: 1 | ||
| Show-ahead 28 | Speed | wrreq / rdreq to full: 1 |
| wrreq to empty: 3 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| wrreq to q[]: 3 | ||
| rdreq to q[]: 1 | ||
| Area | wrreq / rdreq to full: 1 | |
| wrreq to empty: 2 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| wrreq to q[]: 2 | ||
| rdreq to q[]: 1 |
| Output Mode | Optimization Option 29 | Output Latency (in number of clock cycles) |
|---|---|---|
| Normal 30 | Speed | wrreq / rdreq to full: 1 |
| wrreq to empty: 1 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| rdreq to q[]: 1 | ||
| Area | wrreq / rdreq to full: 1 | |
| wrreq / rdreq to empty : 1 | ||
| wrreq / rdreq to usedw[] : 1 | ||
| rdreq to q[]: 1 | ||
| Show-ahead 30 | Speed | wrreq / rdreq to full: 1 |
| wrreq to empty: 1 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| wrreq to q[]: 1 | ||
| rdreq to q[]: 1 | ||
| Area | wrreq / rdreq to full: 1 | |
| wrreq to empty: 1 | ||
| rdreq to empty: 1 | ||
| wrreq / rdreq to usedw[]: 1 | ||
| wrreq to q[]: 1 | ||
| rdreq to q[]: 1 |
| Output Latency (in number of clock cycles) |
|---|
| wrreq to wrfull: 1 wrclk |
| wrreq to rdfull: 2 wrclk cycles + following n rdclk 31 |
| wrreq to wrempty: 1 wrclk |
| wrreq to rdempty: 2 wrclk 32 + following n rdclk 32 |
| wrreq to wrusedw[]: 2 wrclk |
| wrreq to rdusedw[]: 2 wrclk + following n + 1 rdclk 32 |
| wrreq to q[]: 1 wrclk + following 1 rdclk 32 |
| rdreq to rdempty: 1 rdclk |
| rdreq to wrempty: 1 rdclk + following n wrclk 32 |
| rdreq to rfull: 1 rdclk |
| rdreq to wrfull: 1 rdclk + following n wrclk 32 |
| rdreq to rdusedw[]: 2 rdclk |
| rdreq to wrusedw[]: 1 rdclk + following n + 1 wrclk 32 |
| rdreq to q[]: 1 rdclk |
27 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER
parameter to ON.
Setting the parameter to OFF is equivalent to area optimization.
28 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode, the
parameter is set to ON.
29 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER
parameter to ON.
Setting the parameter to OFF is equivalent to area optimization.
30 Normal output mode is equivalent to setting the LPM_SHOWAHEAD parameter to OFF. For Show-ahead mode,
the parameter is set to ON.
31 The number of n cycles for rdclk and wrclk is equivalent to the number of synchronization stages and are related to the WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters. For more information about how the actual synchronization stage (n) is related to the parameters set for different target device, refer to FIFO Metastability Protection and Related Options
.
32 This is applied only
to Show-ahead output modes. Show-ahead output mode is equivalent to setting the
LPM_SHOWAHEAD
parameter to ON.