Intel Quartus Prime Standard Edition User Guide: Partial Reconfiguration Intel FPGA IP - 2019-04-18

1. Partial Reconfiguration IP Core
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
1.2. Instantiating the Partial Reconfiguration IP Core in the Intel Quartus Prime IP Catalog
1.3. Enable Compression
1.3.1. PR Bitstream Compression and Encryption ( Intel Arria 10 Designs)
1.3.2. Generating an Encrypted PR Bitstream
1.4. Enable Enhanced Decompression
1.5. Data Compression Comparison
1.6. Bitstream Compatibility Check
1.7. Clock-to-Data Ratio (CD Ratio)
1.8. Partial Reconfiguration IP Core Parameters
1.9. Partial Reconfiguration IP Core Ports
1.10. Reconfiguration Sequence
1.11. Slave Interface
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface
1.12.1. Partial Reconfiguration IP Core Timing Specification
1.12.2. Avalon -MM Slave Interface Read and Write Transfer Timing
1.13. Freeze Logic for 28-nm PR Regions
1.14. Data Source Controller
1.15. Standard Partial Reconfiguration Data Interface
1.16. JTAG Debug Mode for Partial Reconfiguration
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1.17. Partial Reconfiguration IP Core User Guide Archives
1.18. Revision History

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