LDPC IP Core User Guide - 2022-04-04

Product Discontinuance Notification
1. LDPC IP EOL
2. About the LDPC IP Core
2.1. LDPC IP Core Features
2.2. LDPC IP Device Family Support
2.3. LDPC IP Core Release Information
2.4. DSP Intel FPGA IP Verification
2.5. LDPC IP Core Performance
3. Getting Started with the LDPC IP Core
3.1. Installing and Licensing Intel FPGA IP Cores
3.1.1. Intel FPGA IP Evaluation Mode
3.1.2. LDPC IP Core Intel FPGA IP Evaluation Mode Timeout Behavior
3.2. IP Catalog and Parameter Editor
3.3. Specifying the IP Core Parameters and Options ( Intel Quartus Prime Pro Edition)
3.3.1. IP Core Generation Output ( Intel Quartus Prime Pro Edition)
3.4. Simulating Intel FPGA IP Cores
4. LDPC IP Core Specifications
4.1. LDPC IP Core Interfaces
4.1.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1.2. Clock and Reset Interfaces
4.1.3. LDPC IP Core Signals
4.1.3.1. LDPC IP Core Backpressure
4.2. LDPC IP Core Parameters
5. Document Revision History
A. LDPC IP Core Document Archive

Back to home page