2.1.2. Programmed Input/Output Design Example Limitation - F-Tile Avalon Streaming IP for PCI Express Design Example fails to write back-to-back transactions correctly. - 2026-02-11

F-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

Version: 25.3

F-Tile Avalon Streaming IP for PCI Express Design Example fails to write back-to-back transactions correctly.

For the PIO design example, there is no support for the back-to-back TLP packets from the host processor.

The design example is intended to handle simple read-write instructions based on the TLP command. TLP transaction of memory write request (MWr) and write the data to the MEM device. As for the TLP transaction of memory read request (MRd), the design will read the data from the MEM device and return completion with data (CplD).

Note: This design example does not include the full feature of the F-Tile Avalon Streaming IP for PCI Express. Hence, it is not suitable for customer design reference.